acs_1.vhd

来自「提供了一个硬判决的viterbi译码器（2」· VHDL 代码 · 共 56 行

--ACS_1.vhd 
--add-compare-select unit of viterbi
--v0.1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity ACS_1 is
	port(
		clk: in std_logic;
		reset: in std_logic;
		rc : in std_logic_vector(1 downto 0);
		im_0: in std_logic_vector(5 downto 0);
		im_2: in std_logic_vector(5 downto 0);
		acs_1: out std_logic;
		om_1: out std_logic_vector(5 downto 0)
		);
end ACS_1;

architecture a of ACS_1 is

begin
	process(clk,reset)
	variable mc_0: std_logic_vector(1 downto 0);
	variable mc_2: std_logic_vector(1 downto 0);
	variable up  : unsigned(5 downto 0);
	variable low : unsigned(5 downto 0);
	begin	
		if rising_edge(clk) then
			if reset='1' then
				mc_0:="00";
				mc_2:="00";
				acs_1<='0';
				om_1<="100000";
			else
			mc_0(0):=(not rc(0)) xor (not rc(1));  
			mc_0(1):=(not rc(0)) and (not rc(1));  
			mc_2(0):=rc(0) xor  rc(1);
			mc_2(1):=rc(0) and  rc(1);
			
			up:=unsigned(im_0)+unsigned(mc_0);
			low:=unsigned(im_2)+unsigned(mc_2);
			
				if up<=low then
					acs_1<='0';
					om_1<=conv_std_logic_vector(up,6);
				else
					acs_1<='1';
					om_1<=conv_std_logic_vector(low,6);
				end if;		
			end if;
		end if;
	end process;
end a;