ceshi.tan.rpt

提供了一个硬判决的viterbi译码器（2

+-------+--------------+------------+-------+---------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To                  ; To Clock ;
+-------+--------------+------------+-------+---------------------+----------+
; N/A   ; None         ; 2.025 ns   ; inp   ; conv_213:inst|df[2] ; clk      ;
; N/A   ; None         ; 1.956 ns   ; reset ; conv_213:inst|df[0] ; clk      ;
; N/A   ; None         ; 1.956 ns   ; reset ; conv_213:inst|df[1] ; clk      ;
; N/A   ; None         ; 1.726 ns   ; reset ; conv_213:inst|df[2] ; clk      ;
+-------+--------------+------------+-------+---------------------+----------+


+--------------------------------------------------------------------------------------+
; tco                                                                                  ;
+-------+--------------+------------+---------------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                      ; To      ; From Clock ;
+-------+--------------+------------+---------------------------+---------+------------+
; N/A   ; None         ; 6.654 ns   ; tr_dff2:inst1|out_outp[1] ; outp[1] ; clk        ;
; N/A   ; None         ; 6.261 ns   ; tr_dff2:inst1|out_outp[0] ; outp[0] ; clk        ;
+-------+--------------+------------+---------------------------+---------+------------+


+----------------------------------------------------------------------------------+
; th                                                                               ;
+---------------+-------------+-----------+-------+---------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To                  ; To Clock ;
+---------------+-------------+-----------+-------+---------------------+----------+
; N/A           ; None        ; -1.616 ns ; reset ; conv_213:inst|df[2] ; clk      ;
; N/A           ; None        ; -1.846 ns ; reset ; conv_213:inst|df[0] ; clk      ;
; N/A           ; None        ; -1.846 ns ; reset ; conv_213:inst|df[1] ; clk      ;
; N/A           ; None        ; -1.915 ns ; inp   ; conv_213:inst|df[2] ; clk      ;
+---------------+-------------+-----------+-------+---------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Oct 02 13:12:05 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ceshi -c ceshi --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "conv_213:inst|df[1]" and destination register "tr_dff2:inst1|out_outp[0]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.845 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N0; Fanout = 2; REG Node = 'conv_213:inst|df[1]'
            Info: 2: + IC(0.387 ns) + CELL(0.458 ns) = 0.845 ns; Loc. = LC_X1_Y30_N6; Fanout = 1; REG Node = 'tr_dff2:inst1|out_outp[0]'
            Info: Total cell delay = 0.458 ns ( 54.20 % )
            Info: Total interconnect delay = 0.387 ns ( 45.80 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.934 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N6; Fanout = 1; REG Node = 'tr_dff2:inst1|out_outp[0]'
                Info: Total cell delay = 1.370 ns ( 46.69 % )
                Info: Total interconnect delay = 1.564 ns ( 53.31 % )
            Info: - Longest clock path from clock "clk" to source register is 2.934 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N0; Fanout = 2; REG Node = 'conv_213:inst|df[1]'
                Info: Total cell delay = 1.370 ns ( 46.69 % )
                Info: Total interconnect delay = 1.564 ns ( 53.31 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "conv_213:inst|df[2]" (data pin = "inp", clock pin = "clk") is 2.025 ns
    Info: + Longest pin to register delay is 4.949 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E19; Fanout = 1; PIN Node = 'inp'
        Info: 2: + IC(3.176 ns) + CELL(0.539 ns) = 4.949 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'conv_213:inst|df[2]'
        Info: Total cell delay = 1.773 ns ( 35.83 % )
        Info: Total interconnect delay = 3.176 ns ( 64.17 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'conv_213:inst|df[2]'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
Info: tco from clock "clk" to destination pin "outp[1]" through register "tr_dff2:inst1|out_outp[1]" is 6.654 ns
    Info: + Longest clock path from clock "clk" to source register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N5; Fanout = 1; REG Node = 'tr_dff2:inst1|out_outp[1]'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.564 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N5; Fanout = 1; REG Node = 'tr_dff2:inst1|out_outp[1]'
        Info: 2: + IC(1.160 ns) + CELL(2.404 ns) = 3.564 ns; Loc. = PIN_M16; Fanout = 0; PIN Node = 'outp[1]'
        Info: Total cell delay = 2.404 ns ( 67.45 % )
        Info: Total interconnect delay = 1.160 ns ( 32.55 % )
Info: th for register "conv_213:inst|df[2]" (data pin = "reset", clock pin = "clk") is -1.616 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'conv_213:inst|df[2]'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.650 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E20; Fanout = 3; PIN Node = 'reset'
        Info: 2: + IC(3.193 ns) + CELL(0.223 ns) = 4.650 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'conv_213:inst|df[2]'
        Info: Total cell delay = 1.457 ns ( 31.33 % )
        Info: Total interconnect delay = 3.193 ns ( 68.67 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Oct 02 13:12:06 2006
    Info: Elapsed time: 00:00:01