pwm_led.map.rpt
来自「一个霹雳灯的Verilog源程序」· RPT 代码 · 共 540 行 · 第 1/3 页
RPT
540 行
Analysis & Synthesis report for pwm_led
Wed Aug 23 21:47:31 2006
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Registers Protected by SYN_PRESERVE, DONT_TOUCH
8. User-Specified and Inferred Latches
9. General Register Statistics
10. Multiplexer Restructuring Statistics (Restructuring Performed)
11. Parameter Settings for User Entity Instance: led:led_0
12. Parameter Settings for User Entity Instance: led:led_0|pwm:pwm_x
13. Parameter Settings for User Entity Instance: led:led_1
14. Parameter Settings for User Entity Instance: led:led_1|pwm:pwm_x
15. Parameter Settings for User Entity Instance: led:led_2
16. Parameter Settings for User Entity Instance: led:led_2|pwm:pwm_x
17. Parameter Settings for User Entity Instance: led:led_3
18. Parameter Settings for User Entity Instance: led:led_3|pwm:pwm_x
19. Parameter Settings for User Entity Instance: led:led_4
20. Parameter Settings for User Entity Instance: led:led_4|pwm:pwm_x
21. Parameter Settings for User Entity Instance: led:led_5
22. Parameter Settings for User Entity Instance: led:led_5|pwm:pwm_x
23. Parameter Settings for User Entity Instance: led:led_6
24. Parameter Settings for User Entity Instance: led:led_6|pwm:pwm_x
25. Parameter Settings for User Entity Instance: led:led_7
26. Parameter Settings for User Entity Instance: led:led_7|pwm:pwm_x
27. Analysis & Synthesis Equations
28. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Aug 23 21:47:31 2006 ;
; Quartus II Version ; 5.0 Build 171 11/03/2005 SP 2 SJ Full Version ;
; Revision Name ; pwm_led ;
; Top-level Entity Name ; pwm_led ;
; Family ; Cyclone II ;
; Total combinational functions ; 187 ;
; Total registers ; 97 ;
; Total pins ; 9 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+-----------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; pwm_led ; pwm_led ;
; Family name ; Cyclone II ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; Maximum DSP Block Usage ; -1 ; -1 ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+--------------------------------------------------------------------+--------------+---------------+
+-------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+-------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+-------------------------------------+
; ../../test/pwm_led.v ; yes ; User Verilog HDL File ; E:/zhangwei/fpga_pro/test/pwm_led.v ;
+----------------------------------+-----------------+------------------------+-------------------------------------+
+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------+
; Resource ; Usage ;
+---------------------------------------------+------------+
; Total combinational functions ; 187 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 96 ;
; -- 3 input functions ; 42 ;
; -- <=2 input functions ; 49 ;
; -- Combinational cells for routing ; 0 ;
; Logic elements by mode ; ;
; -- normal mode ; 109 ;
; -- arithmetic mode ; 78 ;
; Total registers ; 97 ;
; I/O pins ; 9 ;
; Maximum fan-out node ; scaler[18] ;
; Maximum fan-out ; 65 ;
; Total fan-out ; 903 ;
; Average fan-out ; 3.08 ;
+---------------------------------------------+------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+
; |pwm_led ; 187 (44) ; 97 (27) ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; |pwm_led ;
; |led:led_0| ; 18 (12) ; 8 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_0 ;
; |pwm:pwm_x| ; 6 (6) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_0|pwm:pwm_x ;
; |led:led_1| ; 17 (12) ; 8 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_1 ;
; |pwm:pwm_x| ; 5 (5) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_1|pwm:pwm_x ;
; |led:led_2| ; 17 (12) ; 8 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_2 ;
; |pwm:pwm_x| ; 5 (5) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_2|pwm:pwm_x ;
; |led:led_3| ; 17 (12) ; 8 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_3 ;
; |pwm:pwm_x| ; 5 (5) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_3|pwm:pwm_x ;
; |led:led_4| ; 17 (12) ; 8 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_4 ;
; |pwm:pwm_x| ; 5 (5) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_4|pwm:pwm_x ;
; |led:led_5| ; 17 (12) ; 8 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pwm_led|led:led_5 ;
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?