pwm_led.tan.rpt

来自「一个霹雳灯的Verilog源程序」· RPT 代码 · 共 396 行 · 第 1/5 页

    Warning: Node "tick[4]" is a latch
    Warning: Node "tick[5]" is a latch
    Warning: Node "tick[6]" is a latch
    Warning: Node "tick[7]" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "tick[7]"
Info: Found combinational loop of 1 nodes
    Info: Node "tick[6]"
Info: Found combinational loop of 1 nodes
    Info: Node "tick[5]"
Info: Found combinational loop of 1 nodes
    Info: Node "tick[4]"
Info: Found combinational loop of 1 nodes
    Info: Node "tick[3]"
Info: Found combinational loop of 1 nodes
    Info: Node "tick[2]"
Info: Found combinational loop of 1 nodes
    Info: Node "tick[1]"
Info: Found combinational loop of 1 nodes
    Info: Node "tick[0]"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "scaler[18]" as buffer
    Info: Detected ripple clock "scaler[5]" as buffer
Info: Clock "clk" has Internal fmax of 191.61 MHz between source register "lscaler[0]" and destination register "led:led_2|LRC[1]" (period= 5.219 ns)
    Info: + Longest register to register delay is 5.001 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y1_N15; Fanout = 3; REG Node = 'lscaler[0]'
        Info: 2: + IC(0.312 ns) + CELL(0.428 ns) = 0.740 ns; Loc. = LCCOMB_X42_Y1_N2; Fanout = 1; COMB Node = 'reduce_nor~22'
        Info: 3: + IC(0.951 ns) + CELL(0.000 ns) = 1.691 ns; Loc. = CLKCTRL_G14; Fanout = 16; COMB Node = 'reduce_nor~22clkctrl'
        Info: 4: + IC(0.000 ns) + CELL(1.635 ns) = 3.326 ns; Loc. = LCCOMB_X44_Y2_N2; Fanout = 9; COMB LOOP Node = 'tick[2]'
            Info: Loc. = LCCOMB_X44_Y2_N2; Node "tick[2]"
        Info: 5: + IC(0.301 ns) + CELL(0.428 ns) = 4.055 ns; Loc. = LCCOMB_X44_Y2_N8; Fanout = 6; COMB Node = 'led:led_2|LRC[0]~220'
        Info: 6: + IC(0.273 ns) + CELL(0.673 ns) = 5.001 ns; Loc. = LCFF_X44_Y2_N17; Fanout = 5; REG Node = 'led:led_2|LRC[1]'
        Info: Total cell delay = 3.164 ns ( 63.27 % )
        Info: Total interconnect delay = 1.837 ns ( 36.73 % )
    Info: - Smallest clock skew is 0.001 ns
        Info: + Shortest clock path from clock "clk" to destination register is 4.955 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.050 ns) + CELL(0.803 ns) = 2.916 ns; Loc. = LCFF_X64_Y19_N19; Fanout = 2; REG Node = 'scaler[18]'
            Info: 4: + IC(0.449 ns) + CELL(0.000 ns) = 3.365 ns; Loc. = CLKCTRL_G4; Fanout = 64; COMB Node = 'scaler[18]~clkctrl'
            Info: 5: + IC(1.042 ns) + CELL(0.548 ns) = 4.955 ns; Loc. = LCFF_X44_Y2_N17; Fanout = 5; REG Node = 'led:led_2|LRC[1]'
            Info: Total cell delay = 2.296 ns ( 46.34 % )
            Info: Total interconnect delay = 2.659 ns ( 53.66 % )
        Info: - Longest clock path from clock "clk" to source register is 4.954 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.050 ns) + CELL(0.803 ns) = 2.916 ns; Loc. = LCFF_X64_Y19_N19; Fanout = 2; REG Node = 'scaler[18]'
            Info: 4: + IC(0.449 ns) + CELL(0.000 ns) = 3.365 ns; Loc. = CLKCTRL_G4; Fanout = 64; COMB Node = 'scaler[18]~clkctrl'
            Info: 5: + IC(1.041 ns) + CELL(0.548 ns) = 4.954 ns; Loc. = LCFF_X42_Y1_N15; Fanout = 3; REG Node = 'lscaler[0]'
            Info: Total cell delay = 2.296 ns ( 46.35 % )
            Info: Total interconnect delay = 2.658 ns ( 53.65 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk" to destination pin "led[0]" through register "led:led_0|pwm:pwm_x|pwm_out" is 9.587 ns
    Info: + Longest clock path from clock "clk" to source register is 5.192 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.049 ns) + CELL(0.803 ns) = 2.915 ns; Loc. = LCFF_X64_Y20_N25; Fanout = 3; REG Node = 'scaler[5]'
        Info: 4: + IC(0.686 ns) + CELL(0.000 ns) = 3.601 ns; Loc. = CLKCTRL_G5; Fanout = 14; COMB Node = 'scaler[5]~clkctrl'
        Info: 5: + IC(1.043 ns) + CELL(0.548 ns) = 5.192 ns; Loc. = LCFF_X45_Y1_N11; Fanout = 2; REG Node = 'led:led_0|pwm:pwm_x|pwm_out'
        Info: Total cell delay = 2.296 ns ( 44.22 % )
        Info: Total interconnect delay = 2.896 ns ( 55.78 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Longest register to pin delay is 4.140 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y1_N11; Fanout = 2; REG Node = 'led:led_0|pwm:pwm_x|pwm_out'
        Info: 2: + IC(1.602 ns) + CELL(2.538 ns) = 4.140 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'led[0]'
        Info: Total cell delay = 2.538 ns ( 61.30 % )
        Info: Total interconnect delay = 1.602 ns ( 38.70 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings
    Info: Processing ended: Wed Aug 23 21:48:19 2006
    Info: Elapsed time: 00:00:01