pwm_led.fit.qmsg

一个霹雳灯的Verilog源程序

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.963 ns register register " "Info: Estimated most critical path is register to register delay of 4.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lscaler\[0\] 1 REG LAB_X42_Y1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X42_Y1; Fanout = 3; REG Node = 'lscaler\[0\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { lscaler[0] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.183 ns) + CELL(0.447 ns) 0.630 ns reduce_nor~22 2 COMB LAB_X42_Y1 1 " "Info: 2: + IC(0.183 ns) + CELL(0.447 ns) = 0.630 ns; Loc. = LAB_X42_Y1; Fanout = 1; COMB Node = 'reduce_nor~22'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.630 ns" { lscaler[0] reduce_nor~22 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.225 ns) + CELL(0.000 ns) 1.855 ns reduce_nor~22clkctrl 3 COMB CLKCTRL_G14 16 " "Info: 3: + IC(1.225 ns) + CELL(0.000 ns) = 1.855 ns; Loc. = CLKCTRL_G14; Fanout = 16; COMB Node = 'reduce_nor~22clkctrl'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "1.225 ns" { reduce_nor~22 reduce_nor~22clkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.280 ns) 3.470 ns tick\[0\] 4 COMB LAB_X43_Y1 9 " "Info: 4: + IC(1.335 ns) + CELL(0.280 ns) = 3.470 ns; Loc. = LAB_X43_Y1; Fanout = 9; COMB Node = 'tick\[0\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "1.615 ns" { reduce_nor~22clkctrl tick[0] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.153 ns) 4.042 ns led:led_0\|LRC\[0\]~220 5 COMB LAB_X43_Y1 6 " "Info: 5: + IC(0.419 ns) + CELL(0.153 ns) = 4.042 ns; Loc. = LAB_X43_Y1; Fanout = 6; COMB Node = 'led:led_0\|LRC\[0\]~220'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.572 ns" { tick[0] led:led_0|LRC[0]~220 } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 202 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.673 ns) 4.963 ns led:led_0\|LRC\[5\] 6 REG LAB_X43_Y1 4 " "Info: 6: + IC(0.248 ns) + CELL(0.673 ns) = 4.963 ns; Loc. = LAB_X43_Y1; Fanout = 4; REG Node = 'led:led_0\|LRC\[5\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.921 ns" { led:led_0|LRC[0]~220 led:led_0|LRC[5] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 202 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.553 ns 31.29 % " "Info: Total cell delay = 1.553 ns ( 31.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.410 ns 68.71 % " "Info: Total interconnect delay = 3.410 ns ( 68.71 % )" {  } {  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.963 ns" { lscaler[0] reduce_nor~22 reduce_nor~22clkctrl tick[0] led:led_0|LRC[0]~220 led:led_0|LRC[5] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C35F672C6 " "Warning: Timing characteristics of device EP2C35F672C6 are preliminary" {  } {  } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[0\] 0 " "Warning: Pin \"led\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[1\] 0 " "Warning: Pin \"led\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[2\] 0 " "Warning: Pin \"led\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[3\] 0 " "Warning: Pin \"led\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[4\] 0 " "Warning: Pin \"led\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[5\] 0 " "Warning: Pin \"led\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[6\] 0 " "Warning: Pin \"led\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "led\[7\] 0 " "Warning: Pin \"led\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0}  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 10 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 23 21:47:57 2006 " "Info: Processing ended: Wed Aug 23 21:47:57 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Info: Elapsed time: 00:00:24" {  } {  } 0}  } {  } 0}