pwm_led.fit.qmsg

一个霹雳灯的Verilog源程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 23 21:47:33 2006 " "Info: Processing started: Wed Aug 23 21:47:33 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off pwm_led -c pwm_led " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pwm_led -c pwm_led" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "pwm_led EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"pwm_led\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0}  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { clk } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" { Floorplan "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" "" { clk } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "scaler\[18\]  " "Info: Automatically promoted node scaler\[18\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "scaler\[18\]~286 " "Info: Destination node scaler\[18\]~286" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scaler\[18\]~286" } } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { scaler[18]~286 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" { Floorplan "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" "" { scaler[18]~286 } "NODE_NAME" } }  } 0}  } {  } 0}  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scaler\[18\]" } } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { scaler[18] } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" { Floorplan "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" "" { scaler[18] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "scaler\[5\]  " "Info: Automatically promoted node scaler\[5\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "scaler\[5\]~260 " "Info: Destination node scaler\[5\]~260" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scaler\[5\]~260" } } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { scaler[5]~260 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" { Floorplan "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" "" { scaler[5]~260 } "NODE_NAME" } }  } 0}  } {  } 0}  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scaler\[5\]" } } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { scaler[5] } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" { Floorplan "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" "" { scaler[5] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reduce_nor~22  " "Info: Automatically promoted node reduce_nor~22 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0}  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~22" } } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { reduce_nor~22 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" { Floorplan "E:/zhangwei/fpga_pro/myown/9/pwm_led.fld" "" "" { reduce_nor~22 } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 0}