pwm_led.tan.qmsg

一个霹雳灯的Verilog源程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "scaler\[18\] " "Info: Detected ripple clock \"scaler\[18\]\" as buffer" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scaler\[18\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "scaler\[5\] " "Info: Detected ripple clock \"scaler\[5\]\" as buffer" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scaler\[5\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lscaler\[0\] register led:led_2\|LRC\[1\] 191.61 MHz 5.219 ns Internal " "Info: Clock \"clk\" has Internal fmax of 191.61 MHz between source register \"lscaler\[0\]\" and destination register \"led:led_2\|LRC\[1\]\" (period= 5.219 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.001 ns + Longest register register " "Info: + Longest register to register delay is 5.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lscaler\[0\] 1 REG LCFF_X42_Y1_N15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y1_N15; Fanout = 3; REG Node = 'lscaler\[0\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { lscaler[0] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.312 ns) + CELL(0.428 ns) 0.740 ns reduce_nor~22 2 COMB LCCOMB_X42_Y1_N2 1 " "Info: 2: + IC(0.312 ns) + CELL(0.428 ns) = 0.740 ns; Loc. = LCCOMB_X42_Y1_N2; Fanout = 1; COMB Node = 'reduce_nor~22'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.740 ns" { lscaler[0] reduce_nor~22 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.951 ns) + CELL(0.000 ns) 1.691 ns reduce_nor~22clkctrl 3 COMB CLKCTRL_G14 16 " "Info: 3: + IC(0.951 ns) + CELL(0.000 ns) = 1.691 ns; Loc. = CLKCTRL_G14; Fanout = 16; COMB Node = 'reduce_nor~22clkctrl'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.951 ns" { reduce_nor~22 reduce_nor~22clkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.635 ns) 3.326 ns tick\[2\] 4 COMB LOOP LCCOMB_X44_Y2_N2 9 " "Info: 4: + IC(0.000 ns) + CELL(1.635 ns) = 3.326 ns; Loc. = LCCOMB_X44_Y2_N2; Fanout = 9; COMB LOOP Node = 'tick\[2\]'" { { "Info" "ITDB_PART_OF_SCC" "tick\[2\] LCCOMB_X44_Y2_N2 " "Info: Loc. = LCCOMB_X44_Y2_N2; Node \"tick\[2\]\"" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { tick[2] } "NODE_NAME" } "" } }  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { tick[2] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 26 -1 0 } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "1.635 ns" { reduce_nor~22clkctrl tick[2] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.301 ns) + CELL(0.428 ns) 4.055 ns led:led_2\|LRC\[0\]~220 5 COMB LCCOMB_X44_Y2_N8 6 " "Info: 5: + IC(0.301 ns) + CELL(0.428 ns) = 4.055 ns; Loc. = LCCOMB_X44_Y2_N8; Fanout = 6; COMB Node = 'led:led_2\|LRC\[0\]~220'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.729 ns" { tick[2] led:led_2|LRC[0]~220 } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 202 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.273 ns) + CELL(0.673 ns) 5.001 ns led:led_2\|LRC\[1\] 6 REG LCFF_X44_Y2_N17 5 " "Info: 6: + IC(0.273 ns) + CELL(0.673 ns) = 5.001 ns; Loc. = LCFF_X44_Y2_N17; Fanout = 5; REG Node = 'led:led_2\|LRC\[1\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.946 ns" { led:led_2|LRC[0]~220 led:led_2|LRC[1] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 202 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.164 ns 63.27 % " "Info: Total cell delay = 3.164 ns ( 63.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.837 ns 36.73 % " "Info: Total interconnect delay = 1.837 ns ( 36.73 % )" {  } {  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "5.001 ns" { lscaler[0] reduce_nor~22 reduce_nor~22clkctrl tick[2] led:led_2|LRC[0]~220 led:led_2|LRC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.001 ns" { lscaler[0] reduce_nor~22 reduce_nor~22clkctrl tick[2] led:led_2|LRC[0]~220 led:led_2|LRC[1] } { 0.000ns 0.312ns 0.951ns 0.000ns 0.301ns 0.273ns } { 0.000ns 0.428ns 0.000ns 1.635ns 0.428ns 0.673ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.955 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 4.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { clk } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.803 ns) 2.916 ns scaler\[18\] 3 REG LCFF_X64_Y19_N19 2 " "Info: 3: + IC(1.050 ns) + CELL(0.803 ns) = 2.916 ns; Loc. = LCFF_X64_Y19_N19; Fanout = 2; REG Node = 'scaler\[18\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "1.853 ns" { clk~clkctrl scaler[18] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.000 ns) 3.365 ns scaler\[18\]~clkctrl 4 COMB CLKCTRL_G4 64 " "Info: 4: + IC(0.449 ns) + CELL(0.000 ns) = 3.365 ns; Loc. = CLKCTRL_G4; Fanout = 64; COMB Node = 'scaler\[18\]~clkctrl'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.449 ns" { scaler[18] scaler[18]~clkctrl } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.042 ns) + CELL(0.548 ns) 4.955 ns led:led_2\|LRC\[1\] 5 REG LCFF_X44_Y2_N17 5 " "Info: 5: + IC(1.042 ns) + CELL(0.548 ns) = 4.955 ns; Loc. = LCFF_X44_Y2_N17; Fanout = 5; REG Node = 'led:led_2\|LRC\[1\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "1.590 ns" { scaler[18]~clkctrl led:led_2|LRC[1] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 202 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.296 ns 46.34 % " "Info: Total cell delay = 2.296 ns ( 46.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.659 ns 53.66 % " "Info: Total interconnect delay = 2.659 ns ( 53.66 % )" {  } {  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.955 ns" { clk clk~clkctrl scaler[18] scaler[18]~clkctrl led:led_2|LRC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.955 ns" { clk clk~combout clk~clkctrl scaler[18] scaler[18]~clkctrl led:led_2|LRC[1] } { 0.000ns 0.000ns 0.118ns 1.050ns 0.449ns 1.042ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 4.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { clk } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.803 ns) 2.916 ns scaler\[18\] 3 REG LCFF_X64_Y19_N19 2 " "Info: 3: + IC(1.050 ns) + CELL(0.803 ns) = 2.916 ns; Loc. = LCFF_X64_Y19_N19; Fanout = 2; REG Node = 'scaler\[18\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "1.853 ns" { clk~clkctrl scaler[18] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.000 ns) 3.365 ns scaler\[18\]~clkctrl 4 COMB CLKCTRL_G4 64 " "Info: 4: + IC(0.449 ns) + CELL(0.000 ns) = 3.365 ns; Loc. = CLKCTRL_G4; Fanout = 64; COMB Node = 'scaler\[18\]~clkctrl'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.449 ns" { scaler[18] scaler[18]~clkctrl } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.548 ns) 4.954 ns lscaler\[0\] 5 REG LCFF_X42_Y1_N15 3 " "Info: 5: + IC(1.041 ns) + CELL(0.548 ns) = 4.954 ns; Loc. = LCFF_X42_Y1_N15; Fanout = 3; REG Node = 'lscaler\[0\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "1.589 ns" { scaler[18]~clkctrl lscaler[0] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.296 ns 46.35 % " "Info: Total cell delay = 2.296 ns ( 46.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.658 ns 53.65 % " "Info: Total interconnect delay = 2.658 ns ( 53.65 % )" {  } {  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.954 ns" { clk clk~clkctrl scaler[18] scaler[18]~clkctrl lscaler[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.954 ns" { clk clk~combout clk~clkctrl scaler[18] scaler[18]~clkctrl lscaler[0] } { 0.000ns 0.000ns 0.118ns 1.050ns 0.449ns 1.041ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } }  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.955 ns" { clk clk~clkctrl scaler[18] scaler[18]~clkctrl led:led_2|LRC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.955 ns" { clk clk~combout clk~clkctrl scaler[18] scaler[18]~clkctrl led:led_2|LRC[1] } { 0.000ns 0.000ns 0.118ns 1.050ns 0.449ns 1.042ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.954 ns" { clk clk~clkctrl scaler[18] scaler[18]~clkctrl lscaler[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.954 ns" { clk clk~combout clk~clkctrl scaler[18] scaler[18]~clkctrl lscaler[0] } { 0.000ns 0.000ns 0.118ns 1.050ns 0.449ns 1.041ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns + " "Info: + Micro clock to output delay of source is 0.255 ns" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 202 -1 0 } }  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "5.001 ns" { lscaler[0] reduce_nor~22 reduce_nor~22clkctrl tick[2] led:led_2|LRC[0]~220 led:led_2|LRC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.001 ns" { lscaler[0] reduce_nor~22 reduce_nor~22clkctrl tick[2] led:led_2|LRC[0]~220 led:led_2|LRC[1] } { 0.000ns 0.312ns 0.951ns 0.000ns 0.301ns 0.273ns } { 0.000ns 0.428ns 0.000ns 1.635ns 0.428ns 0.673ns } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.955 ns" { clk clk~clkctrl scaler[18] scaler[18]~clkctrl led:led_2|LRC[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.955 ns" { clk clk~combout clk~clkctrl scaler[18] scaler[18]~clkctrl led:led_2|LRC[1] } { 0.000ns 0.000ns 0.118ns 1.050ns 0.449ns 1.042ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.954 ns" { clk clk~clkctrl scaler[18] scaler[18]~clkctrl lscaler[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.954 ns" { clk clk~combout clk~clkctrl scaler[18] scaler[18]~clkctrl lscaler[0] } { 0.000ns 0.000ns 0.118ns 1.050ns 0.449ns 1.041ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led\[0\] led:led_0\|pwm:pwm_x\|pwm_out 9.587 ns register " "Info: tco from clock \"clk\" to destination pin \"led\[0\]\" through register \"led:led_0\|pwm:pwm_x\|pwm_out\" is 9.587 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.192 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.192 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { clk } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 19 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 19; COMB Node = 'clk~clkctrl'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.049 ns) + CELL(0.803 ns) 2.915 ns scaler\[5\] 3 REG LCFF_X64_Y20_N25 3 " "Info: 3: + IC(1.049 ns) + CELL(0.803 ns) = 2.915 ns; Loc. = LCFF_X64_Y20_N25; Fanout = 3; REG Node = 'scaler\[5\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "1.852 ns" { clk~clkctrl scaler[5] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.686 ns) + CELL(0.000 ns) 3.601 ns scaler\[5\]~clkctrl 4 COMB CLKCTRL_G5 14 " "Info: 4: + IC(0.686 ns) + CELL(0.000 ns) = 3.601 ns; Loc. = CLKCTRL_G5; Fanout = 14; COMB Node = 'scaler\[5\]~clkctrl'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "0.686 ns" { scaler[5] scaler[5]~clkctrl } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.548 ns) 5.192 ns led:led_0\|pwm:pwm_x\|pwm_out 5 REG LCFF_X45_Y1_N11 2 " "Info: 5: + IC(1.043 ns) + CELL(0.548 ns) = 5.192 ns; Loc. = LCFF_X45_Y1_N11; Fanout = 2; REG Node = 'led:led_0\|pwm:pwm_x\|pwm_out'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "1.591 ns" { scaler[5]~clkctrl led:led_0|pwm:pwm_x|pwm_out } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 243 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.296 ns 44.22 % " "Info: Total cell delay = 2.296 ns ( 44.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.896 ns 55.78 % " "Info: Total interconnect delay = 2.896 ns ( 55.78 % )" {  } {  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "5.192 ns" { clk clk~clkctrl scaler[5] scaler[5]~clkctrl led:led_0|pwm:pwm_x|pwm_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.192 ns" { clk clk~combout clk~clkctrl scaler[5] scaler[5]~clkctrl led:led_0|pwm:pwm_x|pwm_out } { 0.000ns 0.000ns 0.118ns 1.049ns 0.686ns 1.043ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns + " "Info: + Micro clock to output delay of source is 0.255 ns" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 243 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.140 ns + Longest register pin " "Info: + Longest register to pin delay is 4.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led:led_0\|pwm:pwm_x\|pwm_out 1 REG LCFF_X45_Y1_N11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y1_N11; Fanout = 2; REG Node = 'led:led_0\|pwm:pwm_x\|pwm_out'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "" { led:led_0|pwm:pwm_x|pwm_out } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 243 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.602 ns) + CELL(2.538 ns) 4.140 ns led\[0\] 2 PIN PIN_AE22 0 " "Info: 2: + IC(1.602 ns) + CELL(2.538 ns) = 4.140 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'led\[0\]'" {  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.140 ns" { led:led_0|pwm:pwm_x|pwm_out led[0] } "NODE_NAME" } "" } } { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.538 ns 61.30 % " "Info: Total cell delay = 2.538 ns ( 61.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.602 ns 38.70 % " "Info: Total interconnect delay = 1.602 ns ( 38.70 % )" {  } {  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.140 ns" { led:led_0|pwm:pwm_x|pwm_out led[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.140 ns" { led:led_0|pwm:pwm_x|pwm_out led[0] } { 0.000ns 1.602ns } { 0.000ns 2.538ns } } }  } 0}  } { { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "5.192 ns" { clk clk~clkctrl scaler[5] scaler[5]~clkctrl led:led_0|pwm:pwm_x|pwm_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.192 ns" { clk clk~combout clk~clkctrl scaler[5] scaler[5]~clkctrl led:led_0|pwm:pwm_x|pwm_out } { 0.000ns 0.000ns 0.118ns 1.049ns 0.686ns 1.043ns } { 0.000ns 0.945ns 0.000ns 0.803ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/myown/9/db/pwm_led_cmp.qrpt" Compiler "pwm_led" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/myown/9/db/pwm_led.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/myown/9/" "" "4.140 ns" { led:led_0|pwm:pwm_x|pwm_out led[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.140 ns" { led:led_0|pwm:pwm_x|pwm_out led[0] } { 0.000ns 1.602ns } { 0.000ns 2.538ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 23 21:48:19 2006 " "Info: Processing ended: Wed Aug 23 21:48:19 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}