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📄 pwm_led.map.qmsg

📁 一个霹雳灯的Verilog源程序
💻 QMSG
📖 第 1 页 / 共 3 页
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{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(53) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(53): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 53 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(54) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(54): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(55) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(55): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 55 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(56) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(56): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 56 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(57) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(57): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 57 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(58) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(58): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 58 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(59) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(59): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(60) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(60): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 60 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(61) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(61): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 61 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(62) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(62): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(63) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(63): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(64) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(64): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 64 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(65) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(65): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(66) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(66): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(67) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(67): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(68) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(68): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 68 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(69) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(69): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 69 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 5 pwm_led.v(70) " "Warning: (10271) Verilog HDL Case Statement warning at pwm_led.v(70): size of case item expression (32) exceeds the size of the case expression (5)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 70 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "tick pwm_led.v(36) " "Warning: Verilog HDL Always Construct warning at pwm_led.v(36): variable \"tick\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"tick\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 36 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:led_0 " "Info: Elaborating entity \"led\" for hierarchy \"led:led_0\"" {  } { { "../../test/pwm_led.v" "led_0" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 135 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 pwm_led.v(206) " "Warning: Verilog HDL assignment warning at pwm_led.v(206): truncated value with size 32 to match size of target (1)" {  } { { "../../test/pwm_led.v" "" { Text "E:/zhangwei/fpga_pro/test/pwm_led.v" 206 0 0 } }  } 0}

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