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</style></HEAD><BODY align=left style='background-color: #ffffff;'><DIV align=left><TABLE width=95% border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - NCO Compiler MegaCore Function v2.2.2</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width=60%><TR><TD><B>Entity Name</B></TD><TD>nco_st</TD></TR><TR><TD><B>Variation Name</B></TD><TD>nco</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>E:\zhangwei\fpga_pro\myown\9</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>IP Toolbench is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width=100%><TR align=left><TH align=left align=top width=25%><B>File</B></TH><TH align=left><B>Description</B></TH></TR><TR><TD>nco.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>nco_inst.v</TD><TD>Verilog HDL sample instantiation file</TD></TR><TR><TD>nco.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>nco.inc</TD><TD>An AHDL include declaration file for the MegaCore function variation. Include this file with any AHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>nco_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>nco.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>nco_st.v</TD><TD>Generated NCO synthesizable netlist. This file is required for Quartus II synthesis. It will be added to your Quartus II project</TD></TR><TR><TD>nco.vo</TD><TD>Verilog HDL IP Functional Simulation model</TD></TR><TR><TD>nco_tb.v</TD><TD>Verilog HDL Testbench</TD></TR><TR><TD>nco_vo_msim.tcl</TD><TD>Modelsim TCL Script to run the Verilog HDL IP Functional Simulation model and generated Verilog HDL testbench in the Modelsim simulation software</TD></TR><TR><TD>nco_wave.do</TD><TD>Modelsim Waveform File</TD></TR><TR><TD>nco_model.m</TD><TD>Matlab m-file describing a Matlab bit-accurate model.</TD></TR><TR><TD>nco_tb.m</TD><TD>Matlab Testbench</TD></TR><TR><TD>nco_sin.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>nco_cos.hex</TD><TD>Intel Hex-format ROM initialization file.</TD></TR><TR><TD>nco.vec</TD><TD>Quartus Vector File.</TD></TR><TR><TD>nco.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Direction</B></TH><TH align=left><B>Width</B></TH></TR><TR><TD>phi_inc_i</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>fsin_o</TD><TD>OUTPUT</TD><TD>18</TD></TR><TR><TD>fcos_o</TD><TD>OUTPUT</TD><TD>18</TD></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>clken</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_ready</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
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