statuscontrol.vhd

FPGA设计频率计全套资料

--版本号 20070726
--状态机控制程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY STATUSCONTROL IS
PORT(  
       RESET:IN STD_LOGIC;
       CLK:IN STD_LOGIC;
       CLKTESTED,CLKTESTED10:IN STD_LOGIC;
       CLK1HZ,CLK10HZ,CLK100HZ,CLK1KHZ,CLK10KHZ,CLK100KHZ,CLK1MHZ,CLK10MHZ:IN STD_LOGIC;
       LOW,OVER:IN STD_LOGIC;

       OVERH,OVERL:OUT STD_LOGIC;
       DUTYOVER:OUT STD_LOGIC;
       FRECODE:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0);
       DEVIDEFRE10:BUFFER STD_LOGIC;
      -- DEVIDEFRE100:BUFFER STD_LOGIC;
       TIMEBASE:OUT STD_LOGIC;
       TIMECOUNTER:OUT STD_LOGIC
     );
END ENTITY;

ARCHITECTURE MEALYMACHINE OF STATUSCONTROL IS

TYPE STATUS IS(F10M,F1M,F100K,P1MS,P10MS,P100MS,P1S,P10S,OVERFLOWH,OVERFLOWL);
SIGNAL STATE:STATUS;

BEGIN

PROCESS(CLK,RESET)
BEGIN
IF(RESET='1') THEN
   STATE<=F10M;
ELSIF CLK'EVENT AND CLK='1' THEN
   CASE STATE IS
 WHEN F10M=>
     	IF(OVER='1') THEN
       	 	STATE<=OVERFLOWH;
   		ELSIF (LOW='1') THEN
     		STATE<=F1M;
   		ELSE 
     		STATE<=F10M;
        END IF;
WHEN F1M=>
     	IF(OVER='1') THEN
       	 	STATE<=F10M;
   		ELSIF (LOW='1') THEN
     		STATE<=F100K;
   		ELSE 
     		STATE<=F1M;
        END IF;
WHEN F100K=>
     	IF(OVER='1') THEN
       	 	STATE<=F1M;
   		ELSIF (LOW='1') THEN
     		STATE<=P1MS;
   		ELSE 
     		STATE<=F100K;
        END IF;
WHEN P1MS=>
     	IF(OVER='1') THEN
       	 	STATE<=P10MS;
   		ELSIF (LOW='1') THEN
     		STATE<=F100K;
   		ELSE 
     		STATE<=P10MS;
        END IF;
WHEN P10MS=>
     	IF(OVER='1') THEN
       	 	STATE<=P100MS;
   		ELSIF (LOW='1') THEN
     		STATE<=P1MS;
   		ELSE 
     		STATE<=P10MS;
        END IF;
WHEN P100MS=>
     	IF(OVER='1') THEN
       	 	STATE<=P1S;
   		ELSIF (LOW='1') THEN
     		STATE<=P10MS;
   		ELSE 
     		STATE<=P100MS;
        END IF;
WHEN P1S=>
     	IF(OVER='1') THEN
       	 	STATE<=P10S;
   		ELSIF (LOW='1') THEN
     		STATE<=P100MS;
   		ELSE 
     		STATE<=P1S;
        END IF;
WHEN P10S=>
     	IF(OVER='1') THEN
       	 	STATE<=OVERFLOWL;
   		ELSIF (LOW='1') THEN
     		STATE<=P1S;
   		ELSE 
     		STATE<=P10S;
        END IF;
WHEN OVERFLOWH=>
   		IF LOW='1' THEN
			STATE<=F1M;
		ELSE
			STATE<=OVERFLOWH;
		END IF;
WHEN OVERFLOWL=>
   		IF LOW='1' THEN
			STATE<=P1S;
		ELSE
			STATE<=OVERFLOWL;
		END IF;
WHEN OTHERS=>
            STATE<=F10M;
END CASE;
END IF;
END PROCESS;

PROCESS(STATE)
BEGIN
   CASE STATE IS
     	WHEN F10M=>                       --量程为1M~10M
 			TIMEBASE<=CLK100HZ;
			TIMECOUNTER<=CLKTESTED;
			FRECODE<="000";
			OVERH<='0';
			OVERL<='0';
			DEVIDEFRE10<='0';
			--DEVIDEFRE100<='0';
			DUTYOVER<='1';
 	   	WHEN F1M=>							--量程为100K~1M
 			TIMEBASE<=CLK10HZ;
			TIMECOUNTER<=CLKTESTED;
			FRECODE<="001";
			OVERH<='0';
			OVERL<='0';
			DEVIDEFRE10<='0';
		   -- DEVIDEFRE100<='0';
			DUTYOVER<='1';
     	WHEN F100K=>                       --量程为10K~100K
 			TIMEBASE<=CLK1HZ;
			TIMECOUNTER<=CLKTESTED;
			FRECODE<="010";
			OVERH<='0';
			OVERL<='0';
			DEVIDEFRE10<='0';
			--DEVIDEFRE100<='0';
			DUTYOVER<='1';
     	WHEN P1MS=>                       --量程为1K~10K
 			TIMEBASE<=CLKTESTED10;
			TIMECOUNTER<=CLK10MHZ;
			FRECODE<="011";
			OVERH<='0';
			OVERL<='0';
			DEVIDEFRE10<='1';--- 10FENPIN
			--DEVIDEFRE100<='1';
			DUTYOVER<='1';
     	WHEN P10MS=>                     --量程为100~1K
 			TIMEBASE<=CLKTESTED;
			TIMECOUNTER<=CLK10MHZ;
			FRECODE<="100";
			OVERH<='0';
			OVERL<='0';
			DEVIDEFRE10<='0';---  10FENPIN
			--DEVIDEFRE100<='0';
			DUTYOVER<='1';
     	WHEN P100MS=>                 --量程为10~100HZ
 			TIMEBASE<=CLKTESTED;
			TIMECOUNTER<=CLK1MHZ;
			FRECODE<="101";
			OVERH<='0';
			OVERL<='0';
			DEVIDEFRE10<='0';
			--DEVIDEFRE100<='0';
			DUTYOVER<='1';
     	WHEN P1S=>                    --量程为1HZ~10HZ
 			TIMEBASE<=CLKTESTED;
			TIMECOUNTER<=CLK100KHZ;
			FRECODE<="110";
			OVERH<='0';
			OVERL<='0';
			DEVIDEFRE10<='0';
			--DEVIDEFRE100<='0';
			DUTYOVER<='0';
     	WHEN P10S=>                   --量程为0.1HZ~1HZ
 			TIMEBASE<=CLKTESTED;
			TIMECOUNTER<=CLK10KHZ;
			FRECODE<="111";
			OVERH<='0';
			OVERL<='0';
			DEVIDEFRE10<='0';
			--DEVIDEFRE100<='0';
			DUTYOVER<='0';
     	WHEN OVERFLOWH=>             
 			TIMEBASE<=CLK1KHZ;
			TIMECOUNTER<=CLKTESTED;
			FRECODE<="000";
			OVERH<='1';
			OVERL<='0';
			DEVIDEFRE10<='0';
			--DEVIDEFRE100<='0';
			DUTYOVER<='1';
     	WHEN OVERFLOWL=>
 			TIMEBASE<=CLKTESTED;
			TIMECOUNTER<=CLK10KHZ;
			FRECODE<="111";
			OVERH<='0';
			OVERL<='1';
			DEVIDEFRE10<='0';
			--DEVIDEFRE100<='0';
			DUTYOVER<='1';
     	WHEN OTHERS=>
 			--TIMEBASE<=CLK1KHZ;
			--TIMECOUNTER<=CLKTESTED;
			FRECODE<="000";
			OVERH<='0';
			OVERL<='0';
			DEVIDEFRE10<='0';
			--DEVIDEFRE100<='0';
			DUTYOVER<='0';
	    END CASE;
	END PROCESS;

END MEALYMACHINE;