signalltach.vhd

来自「FPGA设计频率计全套资料」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SIGNALLTACH IS
PORT(  CLK:IN STD_LOGIC;
       SIGIN:IN STD_LOGIC;
  
       SIGOUT:OUT STD_LOGIC
    );
END ENTITY;

ARCHITECTURE MEALYMACHINE OF SIGNALLTACH IS

SIGNAL LOCK:STD_LOGIC:='0';
SIGNAL CLKN:STD_LOGIC;

BEGIN
CLKN<=NOT CLK;
PROCESS(CLKN)
BEGIN
IF CLKN'EVENT AND CLKN='1'  THEN
      IF( LOCK='0' AND SIGIN='1') THEN
              SIGOUT<='1';
      ELSE 
              SIGOUT<='0';
      END IF;
      LOCK<=SIGIN;
END IF;             
END PROCESS;

END;