sreg.vhd

来自「FPGA设计频率计全套资料」· VHDL 代码 · 共 39 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SREG IS
  GENERIC(
            K:INTEGER:=40
         );
  PORT( CLK,SEL:IN STD_LOGIC;
        DATAIN:IN STD_LOGIC_VECTOR(K-1 DOWNTO 0);
       --TE:OUT STD_LOGIC_VECTOR(K-1 DOWNTO 0);
        Q:OUT STD_LOGIC);
 END ENTITY;

ARCHITECTURE DATAFLOW OF SREG IS

SIGNAL TEMP:STD_LOGIC_VECTOR(K-1 DOWNTO 0);

BEGIN

--TE<=TEMP;
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
   IF SEL='1' THEN
    TEMP<=DATAIN;
    Q<='0';
   ELSIF SEL='0' THEN
    FOR i IN 0 TO 38 LOOP
        TEMP(i)<=TEMP(i+1);
   END LOOP;
   TEMP(39)<='0';
    Q<=TEMP(0);
END IF;
END IF;
END PROCESS;


END;