frequencycount.tan.qmsg

FPGA设计频率计全套资料

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "20mclk register COUNTER:inst\|OVER register SIGNALLTACH:inst12\|SIGOUT 27.56 MHz 36.278 ns Internal " "Info: Clock \"20mclk\" has Internal fmax of 27.56 MHz between source register \"COUNTER:inst\|OVER\" and destination register \"SIGNALLTACH:inst12\|SIGOUT\" (period= 36.278 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.874 ns + Longest register register " "Info: + Longest register to register delay is 0.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNTER:inst\|OVER 1 REG LC_X26_Y7_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y7_N5; Fanout = 4; REG Node = 'COUNTER:inst\|OVER'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { COUNTER:inst|OVER } "NODE_NAME" } } { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.309 ns) 0.874 ns SIGNALLTACH:inst12\|SIGOUT 2 REG LC_X26_Y7_N8 14 " "Info: 2: + IC(0.565 ns) + CELL(0.309 ns) = 0.874 ns; Loc. = LC_X26_Y7_N8; Fanout = 14; REG Node = 'SIGNALLTACH:inst12\|SIGOUT'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.874 ns" { COUNTER:inst|OVER SIGNALLTACH:inst12|SIGOUT } "NODE_NAME" } } { "SIGNALLTACH.vhd" "" { Text "E:/pinlvji/SIGNALLTACH.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 35.35 % ) " "Info: Total cell delay = 0.309 ns ( 35.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.565 ns ( 64.65 % ) " "Info: Total interconnect delay = 0.565 ns ( 64.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.874 ns" { COUNTER:inst|OVER SIGNALLTACH:inst12|SIGOUT } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.874 ns" { COUNTER:inst|OVER SIGNALLTACH:inst12|SIGOUT } { 0.000ns 0.565ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-17.004 ns - Smallest " "Info: - Smallest clock skew is -17.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "20mclk destination 7.511 ns + Shortest register " "Info: + Shortest clock path from clock \"20mclk\" to destination register is 7.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns 20mclk 1 CLK PIN_16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 1; CLK Node = '20mclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 20mclk } "NODE_NAME" } } { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { 656 -320 -152 672 "20mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.935 ns) 3.290 ns DIV2:inst10\|CLKN 2 REG LC_X8_Y6_N2 21 " "Info: 2: + IC(0.886 ns) + CELL(0.935 ns) = 3.290 ns; Loc. = LC_X8_Y6_N2; Fanout = 21; REG Node = 'DIV2:inst10\|CLKN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.821 ns" { 20mclk DIV2:inst10|CLKN } "NODE_NAME" } } { "DIV2.vhd" "" { Text "E:/pinlvji/DIV2.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.510 ns) + CELL(0.711 ns) 7.511 ns SIGNALLTACH:inst12\|SIGOUT 3 REG LC_X26_Y7_N8 14 " "Info: 3: + IC(3.510 ns) + CELL(0.711 ns) = 7.511 ns; Loc. = LC_X26_Y7_N8; Fanout = 14; REG Node = 'SIGNALLTACH:inst12\|SIGOUT'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.221 ns" { DIV2:inst10|CLKN SIGNALLTACH:inst12|SIGOUT } "NODE_NAME" } } { "SIGNALLTACH.vhd" "" { Text "E:/pinlvji/SIGNALLTACH.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.47 % ) " "Info: Total cell delay = 3.115 ns ( 41.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.396 ns ( 58.53 % ) " "Info: Total interconnect delay = 4.396 ns ( 58.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.511 ns" { 20mclk DIV2:inst10|CLKN SIGNALLTACH:inst12|SIGOUT } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.511 ns" { 20mclk 20mclk~out0 DIV2:inst10|CLKN SIGNALLTACH:inst12|SIGOUT } { 0.000ns 0.000ns 0.886ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "20mclk source 24.515 ns - Longest register " "Info: - Longest clock path from clock \"20mclk\" to source register is 24.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns 20mclk 1 CLK PIN_16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 1; CLK Node = '20mclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 20mclk } "NODE_NAME" } } { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { 656 -320 -152 672 "20mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.935 ns) 3.290 ns DIV2:inst10\|CLKN 2 REG LC_X8_Y6_N2 21 " "Info: 2: + IC(0.886 ns) + CELL(0.935 ns) = 3.290 ns; Loc. = LC_X8_Y6_N2; Fanout = 21; REG Node = 'DIV2:inst10\|CLKN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.821 ns" { 20mclk DIV2:inst10|CLKN } "NODE_NAME" } } { "DIV2.vhd" "" { Text "E:/pinlvji/DIV2.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.467 ns) + CELL(0.935 ns) 7.692 ns FREQUENCY10:inst11\|CLK_OUT 3 REG LC_X10_Y6_N8 12 " "Info: 3: + IC(3.467 ns) + CELL(0.935 ns) = 7.692 ns; Loc. = LC_X10_Y6_N8; Fanout = 12; REG Node = 'FREQUENCY10:inst11\|CLK_OUT'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.402 ns" { DIV2:inst10|CLKN FREQUENCY10:inst11|CLK_OUT } "NODE_NAME" } } { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.846 ns) + CELL(0.935 ns) 12.473 ns FREQUENCY10:inst4\|CLK_OUT 4 REG LC_X26_Y5_N4 7 " "Info: 4: + IC(3.846 ns) + CELL(0.935 ns) = 12.473 ns; Loc. = LC_X26_Y5_N4; Fanout = 7; REG Node = 'FREQUENCY10:inst4\|CLK_OUT'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.781 ns" { FREQUENCY10:inst11|CLK_OUT FREQUENCY10:inst4|CLK_OUT } "NODE_NAME" } } { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.167 ns) + CELL(0.935 ns) 17.575 ns FREQUENCY10:inst5\|CLK_OUT 5 REG LC_X23_Y6_N2 7 " "Info: 5: + IC(4.167 ns) + CELL(0.935 ns) = 17.575 ns; Loc. = LC_X23_Y6_N2; Fanout = 7; REG Node = 'FREQUENCY10:inst5\|CLK_OUT'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.102 ns" { FREQUENCY10:inst4|CLK_OUT FREQUENCY10:inst5|CLK_OUT } "NODE_NAME" } } { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.791 ns) + CELL(0.114 ns) 18.480 ns STATUSCONTROL:inst2\|Selector11~82 6 COMB LC_X24_Y6_N0 1 " "Info: 6: + IC(0.791 ns) + CELL(0.114 ns) = 18.480 ns; Loc. = LC_X24_Y6_N0; Fanout = 1; COMB Node = 'STATUSCONTROL:inst2\|Selector11~82'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.905 ns" { FREQUENCY10:inst5|CLK_OUT STATUSCONTROL:inst2|Selector11~82 } "NODE_NAME" } } { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.590 ns) 20.146 ns STATUSCONTROL:inst2\|Selector11~84 7 COMB LC_X26_Y6_N6 70 " "Info: 7: + IC(1.076 ns) + CELL(0.590 ns) = 20.146 ns; Loc. = LC_X26_Y6_N6; Fanout = 70; COMB Node = 'STATUSCONTROL:inst2\|Selector11~84'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.666 ns" { STATUSCONTROL:inst2|Selector11~82 STATUSCONTROL:inst2|Selector11~84 } "NODE_NAME" } } { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.658 ns) + CELL(0.711 ns) 24.515 ns COUNTER:inst\|OVER 8 REG LC_X26_Y7_N5 4 " "Info: 8: + IC(3.658 ns) + CELL(0.711 ns) = 24.515 ns; Loc. = LC_X26_Y7_N5; Fanout = 4; REG Node = 'COUNTER:inst\|OVER'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.369 ns" { STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|OVER } "NODE_NAME" } } { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.624 ns ( 27.02 % ) " "Info: Total cell delay = 6.624 ns ( 27.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.891 ns ( 72.98 % ) " "Info: Total interconnect delay = 17.891 ns ( 72.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "24.515 ns" { 20mclk DIV2:inst10|CLKN FREQUENCY10:inst11|CLK_OUT FREQUENCY10:inst4|CLK_OUT FREQUENCY10:inst5|CLK_OUT STATUSCONTROL:inst2|Selector11~82 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|OVER } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "24.515 ns" { 20mclk 20mclk~out0 DIV2:inst10|CLKN FREQUENCY10:inst11|CLK_OUT FREQUENCY10:inst4|CLK_OUT FREQUENCY10:inst5|CLK_OUT STATUSCONTROL:inst2|Selector11~82 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|OVER } { 0.000ns 0.000ns 0.886ns 3.467ns 3.846ns 4.167ns 0.791ns 1.076ns 3.658ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.114ns 0.590ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.511 ns" { 20mclk DIV2:inst10|CLKN SIGNALLTACH:inst12|SIGOUT } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.511 ns" { 20mclk 20mclk~out0 DIV2:inst10|CLKN SIGNALLTACH:inst12|SIGOUT } { 0.000ns 0.000ns 0.886ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "24.515 ns" { 20mclk DIV2:inst10|CLKN FREQUENCY10:inst11|CLK_OUT FREQUENCY10:inst4|CLK_OUT FREQUENCY10:inst5|CLK_OUT STATUSCONTROL:inst2|Selector11~82 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|OVER } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "24.515 ns" { 20mclk 20mclk~out0 DIV2:inst10|CLKN FREQUENCY10:inst11|CLK_OUT FREQUENCY10:inst4|CLK_OUT FREQUENCY10:inst5|CLK_OUT STATUSCONTROL:inst2|Selector11~82 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|OVER } { 0.000ns 0.000ns 0.886ns 3.467ns 3.846ns 4.167ns 0.791ns 1.076ns 3.658ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.114ns 0.590ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "SIGNALLTACH.vhd" "" { Text "E:/pinlvji/SIGNALLTACH.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 14 -1 0 } } { "SIGNALLTACH.vhd" "" { Text "E:/pinlvji/SIGNALLTACH.vhd" 9 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.874 ns" { COUNTER:inst|OVER SIGNALLTACH:inst12|SIGOUT } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.874 ns" { COUNTER:inst|OVER SIGNALLTACH:inst12|SIGOUT } { 0.000ns 0.565ns } { 0.000ns 0.309ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.511 ns" { 20mclk DIV2:inst10|CLKN SIGNALLTACH:inst12|SIGOUT } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.511 ns" { 20mclk 20mclk~out0 DIV2:inst10|CLKN SIGNALLTACH:inst12|SIGOUT } { 0.000ns 0.000ns 0.886ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "24.515 ns" { 20mclk DIV2:inst10|CLKN FREQUENCY10:inst11|CLK_OUT FREQUENCY10:inst4|CLK_OUT FREQUENCY10:inst5|CLK_OUT STATUSCONTROL:inst2|Selector11~82 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|OVER } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "24.515 ns" { 20mclk 20mclk~out0 DIV2:inst10|CLKN FREQUENCY10:inst11|CLK_OUT FREQUENCY10:inst4|CLK_OUT FREQUENCY10:inst5|CLK_OUT STATUSCONTROL:inst2|Selector11~82 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|OVER } { 0.000ns 0.000ns 0.886ns 3.467ns 3.846ns 4.167ns 0.791ns 1.076ns 3.658ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.114ns 0.590ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_TEST register COUNTER:inst\|NUM\[8\] register COUNTER:inst\|NUMH\[1\] 131.46 MHz 7.607 ns Internal " "Info: Clock \"CLK_TEST\" has Internal fmax of 131.46 MHz between source register \"COUNTER:inst\|NUM\[8\]\" and destination register \"COUNTER:inst\|NUMH\[1\]\" (period= 7.607 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.346 ns + Longest register register " "Info: + Longest register to register delay is 7.346 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNTER:inst\|NUM\[8\] 1 REG LC_X22_Y8_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y8_N0; Fanout = 6; REG Node = 'COUNTER:inst\|NUM\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { COUNTER:inst|NUM[8] } "NODE_NAME" } } { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.590 ns) 1.901 ns COUNTER:inst\|Equal0~146 2 COMB LC_X21_Y7_N7 1 " "Info: 2: + IC(1.311 ns) + CELL(0.590 ns) = 1.901 ns; Loc. = LC_X21_Y7_N7; Fanout = 1; COMB Node = 'COUNTER:inst\|Equal0~146'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.901 ns" { COUNTER:inst|NUM[8] COUNTER:inst|Equal0~146 } "NODE_NAME" } } { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.442 ns) 3.538 ns COUNTER:inst\|Equal0~147 3 COMB LC_X22_Y9_N1 7 " "Info: 3: + IC(1.195 ns) + CELL(0.442 ns) = 3.538 ns; Loc. = LC_X22_Y9_N1; Fanout = 7; COMB Node = 'COUNTER:inst\|Equal0~147'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.637 ns" { COUNTER:inst|Equal0~146 COUNTER:inst|Equal0~147 } "NODE_NAME" } } { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.114 ns) 5.204 ns COUNTER:inst\|NUMH\[13\]~688 4 COMB LC_X25_Y7_N9 17 " "Info: 4: + IC(1.552 ns) + CELL(0.114 ns) = 5.204 ns; Loc. = LC_X25_Y7_N9; Fanout = 17; COMB Node = 'COUNTER:inst\|NUMH\[13\]~688'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.666 ns" { COUNTER:inst|Equal0~147 COUNTER:inst|NUMH[13]~688 } "NODE_NAME" } } { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.275 ns) + CELL(0.867 ns) 7.346 ns COUNTER:inst\|NUMH\[1\] 5 REG LC_X25_Y8_N3 4 " "Info: 5: + IC(1.275 ns) + CELL(0.867 ns) = 7.346 ns; Loc. = LC_X25_Y8_N3; Fanout = 4; REG Node = 'COUNTER:inst\|NUMH\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.142 ns" { COUNTER:inst|NUMH[13]~688 COUNTER:inst|NUMH[1] } "NODE_NAME" } } { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.013 ns ( 27.40 % ) " "Info: Total cell delay = 2.013 ns ( 27.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.333 ns ( 72.60 % ) " "Info: Total interconnect delay = 5.333 ns ( 72.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.346 ns" { COUNTER:inst|NUM[8] COUNTER:inst|Equal0~146 COUNTER:inst|Equal0~147 COUNTER:inst|NUMH[13]~688 COUNTER:inst|NUMH[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.346 ns" { COUNTER:inst|NUM[8] COUNTER:inst|Equal0~146 COUNTER:inst|Equal0~147 COUNTER:inst|NUMH[13]~688 COUNTER:inst|NUMH[1] } { 0.000ns 1.311ns 1.195ns 1.552ns 1.275ns } { 0.000ns 0.590ns 0.442ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_TEST destination 10.431 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_TEST\" to destination register is 10.431 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_TEST 1 CLK PIN_3 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 7; CLK Node = 'CLK_TEST'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_TEST } "NODE_NAME" } } { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -128 -408 -240 -112 "CLK_TEST" "" } { -32 232 296 -16 "CLK_TEST" "" } { 136 240 328 152 "CLK_TEST" "" } { -136 -240 -176 -120 "CLK_TEST" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.151 ns) + CELL(0.442 ns) 6.062 ns STATUSCONTROL:inst2\|Selector11~84 2 COMB LC_X26_Y6_N6 70 " "Info: 2: + IC(4.151 ns) + CELL(0.442 ns) = 6.062 ns; Loc. = LC_X26_Y6_N6; Fanout = 70; COMB Node = 'STATUSCONTROL:inst2\|Selector11~84'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.593 ns" { CLK_TEST STATUSCONTROL:inst2|Selector11~84 } "NODE_NAME" } } { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.658 ns) + CELL(0.711 ns) 10.431 ns COUNTER:inst\|NUMH\[1\] 3 REG LC_X25_Y8_N3 4 " "Info: 3: + IC(3.658 ns) + CELL(0.711 ns) = 10.431 ns; Loc. = LC_X25_Y8_N3; Fanout = 4; REG Node = 'COUNTER:inst\|NUMH\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.369 ns" { STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUMH[1] } "NODE_NAME" } } { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns ( 25.14 % ) " "Info: Total cell delay = 2.622 ns ( 25.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.809 ns ( 74.86 % ) " "Info: Total interconnect delay = 7.809 ns ( 74.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.431 ns" { CLK_TEST STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUMH[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.431 ns" { CLK_TEST CLK_TEST~out0 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUMH[1] } { 0.000ns 0.000ns 4.151ns 3.658ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_TEST source 10.431 ns - Longest register " "Info: - Longest clock path from clock \"CLK_TEST\" to source register is 10.431 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_TEST 1 CLK PIN_3 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 7; CLK Node = 'CLK_TEST'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_TEST } "NODE_NAME" } } { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -128 -408 -240 -112 "CLK_TEST" "" } { -32 232 296 -16 "CLK_TEST" "" } { 136 240 328 152 "CLK_TEST" "" } { -136 -240 -176 -120 "CLK_TEST" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.151 ns) + CELL(0.442 ns) 6.062 ns STATUSCONTROL:inst2\|Selector11~84 2 COMB LC_X26_Y6_N6 70 " "Info: 2: + IC(4.151 ns) + CELL(0.442 ns) = 6.062 ns; Loc. = LC_X26_Y6_N6; Fanout = 70; COMB Node = 'STATUSCONTROL:inst2\|Selector11~84'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.593 ns" { CLK_TEST STATUSCONTROL:inst2|Selector11~84 } "NODE_NAME" } } { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.658 ns) + CELL(0.711 ns) 10.431 ns COUNTER:inst\|NUM\[8\] 3 REG LC_X22_Y8_N0 6 " "Info: 3: + IC(3.658 ns) + CELL(0.711 ns) = 10.431 ns; Loc. = LC_X22_Y8_N0; Fanout = 6; REG Node = 'COUNTER:inst\|NUM\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.369 ns" { STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUM[8] } "NODE_NAME" } } { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns ( 25.14 % ) " "Info: Total cell delay = 2.622 ns ( 25.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.809 ns ( 74.86 % ) " "Info: Total interconnect delay = 7.809 ns ( 74.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.431 ns" { CLK_TEST STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUM[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.431 ns" { CLK_TEST CLK_TEST~out0 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUM[8] } { 0.000ns 0.000ns 4.151ns 3.658ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.431 ns" { CLK_TEST STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUMH[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.431 ns" { CLK_TEST CLK_TEST~out0 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUMH[1] } { 0.000ns 0.000ns 4.151ns 3.658ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.431 ns" { CLK_TEST STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUM[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.431 ns" { CLK_TEST CLK_TEST~out0 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUM[8] } { 0.000ns 0.000ns 4.151ns 3.658ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.346 ns" { COUNTER:inst|NUM[8] COUNTER:inst|Equal0~146 COUNTER:inst|Equal0~147 COUNTER:inst|NUMH[13]~688 COUNTER:inst|NUMH[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.346 ns" { COUNTER:inst|NUM[8] COUNTER:inst|Equal0~146 COUNTER:inst|Equal0~147 COUNTER:inst|NUMH[13]~688 COUNTER:inst|NUMH[1] } { 0.000ns 1.311ns 1.195ns 1.552ns 1.275ns } { 0.000ns 0.590ns 0.442ns 0.114ns 0.867ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.431 ns" { CLK_TEST STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUMH[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.431 ns" { CLK_TEST CLK_TEST~out0 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUMH[1] } { 0.000ns 0.000ns 4.151ns 3.658ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.431 ns" { CLK_TEST STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUM[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.431 ns" { CLK_TEST CLK_TEST~out0 STATUSCONTROL:inst2|Selector11~84 COUNTER:inst|NUM[8] } { 0.000ns 0.000ns 4.151ns 3.658ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}