frequencycount.tan.qmsg

FPGA设计频率计全套资料

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "30 " "Warning: Found 30 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|Selector10~73 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|Selector10~73\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|Selector10~73" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|Selector10~72 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|Selector10~72\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|Selector10~72" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY10:inst1\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY10:inst1\|CLK_OUT\" as buffer" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY10:inst1\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY10:inst7\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY10:inst7\|CLK_OUT\" as buffer" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY10:inst7\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY10:inst9\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY10:inst9\|CLK_OUT\" as buffer" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY10:inst9\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|Selector10~74 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|Selector10~74\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|Selector10~74" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|Selector10~75 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|Selector10~75\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|Selector10~75" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY10:inst8\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY10:inst8\|CLK_OUT\" as buffer" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY10:inst8\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|Selector11~81 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|Selector11~81\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|Selector11~81" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY10:inst4\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY10:inst4\|CLK_OUT\" as buffer" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY10:inst4\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.p10s " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.p10s\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.p10s" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY10:inst5\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY10:inst5\|CLK_OUT\" as buffer" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY10:inst5\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY10:inst6\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY10:inst6\|CLK_OUT\" as buffer" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY10:inst6\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY10:inst11\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY10:inst11\|CLK_OUT\" as buffer" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY10:inst11\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|Selector11~83 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|Selector11~83\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|Selector11~83" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|WideOr12~13 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|WideOr12~13\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|WideOr12~13" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|Selector11~82 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|Selector11~82\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|Selector11~82" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|Selector10~76 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|Selector10~76\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|Selector10~76" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "STATUSCONTROL:inst2\|Selector11~84 " "Info: Detected gated clock \"STATUSCONTROL:inst2\|Selector11~84\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|Selector11~84" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "COUNTER:inst\|ENTRANSFER " "Info: Detected ripple clock \"COUNTER:inst\|ENTRANSFER\" as buffer" {  } { { "COUNTER.vhd" "" { Text "E:/pinlvji/COUNTER.vhd" 23 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "COUNTER:inst\|ENTRANSFER" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.overflowl " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.overflowl\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.overflowl" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.p1s " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.p1s\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.p1s" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.p100ms " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.p100ms\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.p100ms" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.f1m " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.f1m\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.f1m" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.p10ms " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.p10ms\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.p10ms" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.f100k " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.f100k\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.f100k" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.p1ms " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.p1ms\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.p1ms" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.overflowh " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.overflowh\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.overflowh" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "DIV2:inst10\|CLKN " "Info: Detected ripple clock \"DIV2:inst10\|CLKN\" as buffer" {  } { { "DIV2.vhd" "" { Text "E:/pinlvji/DIV2.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DIV2:inst10\|CLKN" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "STATUSCONTROL:inst2\|STATE.f10m " "Info: Detected ripple clock \"STATUSCONTROL:inst2\|STATE.f10m\" as buffer" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "STATUSCONTROL:inst2\|STATE.f10m" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK_SE register register SREG:inst13\|TEMP\[25\] SREG:inst13\|TEMP\[24\] 275.03 MHz Internal " "Info: Clock \"CLK_SE\" Internal fmax is restricted to 275.03 MHz between source register \"SREG:inst13\|TEMP\[25\]\" and destination register \"SREG:inst13\|TEMP\[24\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.574 ns + Longest register register " "Info: + Longest register to register delay is 1.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SREG:inst13\|TEMP\[25\] 1 REG LC_X22_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y6_N1; Fanout = 1; REG Node = 'SREG:inst13\|TEMP\[25\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SREG:inst13|TEMP[25] } "NODE_NAME" } } { "SREG.vhd" "" { Text "E:/pinlvji/SREG.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.309 ns) 1.574 ns SREG:inst13\|TEMP\[24\] 2 REG LC_X23_Y7_N4 1 " "Info: 2: + IC(1.265 ns) + CELL(0.309 ns) = 1.574 ns; Loc. = LC_X23_Y7_N4; Fanout = 1; REG Node = 'SREG:inst13\|TEMP\[24\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { SREG:inst13|TEMP[25] SREG:inst13|TEMP[24] } "NODE_NAME" } } { "SREG.vhd" "" { Text "E:/pinlvji/SREG.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 19.63 % ) " "Info: Total cell delay = 0.309 ns ( 19.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.265 ns ( 80.37 % ) " "Info: Total interconnect delay = 1.265 ns ( 80.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { SREG:inst13|TEMP[25] SREG:inst13|TEMP[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.574 ns" { SREG:inst13|TEMP[25] SREG:inst13|TEMP[24] } { 0.000ns 1.265ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_SE destination 7.297 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_SE\" to destination register is 7.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_SE 1 CLK PIN_2 41 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 41; CLK Node = 'CLK_SE'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_SE } "NODE_NAME" } } { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -96 -408 -240 -80 "CLK_SE" "" } { 600 864 928 616 "CLK_SE" "" } { -104 -240 -176 -88 "CLK_SE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.117 ns) + CELL(0.711 ns) 7.297 ns SREG:inst13\|TEMP\[24\] 2 REG LC_X23_Y7_N4 1 " "Info: 2: + IC(5.117 ns) + CELL(0.711 ns) = 7.297 ns; Loc. = LC_X23_Y7_N4; Fanout = 1; REG Node = 'SREG:inst13\|TEMP\[24\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.828 ns" { CLK_SE SREG:inst13|TEMP[24] } "NODE_NAME" } } { "SREG.vhd" "" { Text "E:/pinlvji/SREG.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 29.88 % ) " "Info: Total cell delay = 2.180 ns ( 29.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.117 ns ( 70.12 % ) " "Info: Total interconnect delay = 5.117 ns ( 70.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.297 ns" { CLK_SE SREG:inst13|TEMP[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.297 ns" { CLK_SE CLK_SE~out0 SREG:inst13|TEMP[24] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_SE source 7.297 ns - Longest register " "Info: - Longest clock path from clock \"CLK_SE\" to source register is 7.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_SE 1 CLK PIN_2 41 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 41; CLK Node = 'CLK_SE'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_SE } "NODE_NAME" } } { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -96 -408 -240 -80 "CLK_SE" "" } { 600 864 928 616 "CLK_SE" "" } { -104 -240 -176 -88 "CLK_SE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.117 ns) + CELL(0.711 ns) 7.297 ns SREG:inst13\|TEMP\[25\] 2 REG LC_X22_Y6_N1 1 " "Info: 2: + IC(5.117 ns) + CELL(0.711 ns) = 7.297 ns; Loc. = LC_X22_Y6_N1; Fanout = 1; REG Node = 'SREG:inst13\|TEMP\[25\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.828 ns" { CLK_SE SREG:inst13|TEMP[25] } "NODE_NAME" } } { "SREG.vhd" "" { Text "E:/pinlvji/SREG.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 29.88 % ) " "Info: Total cell delay = 2.180 ns ( 29.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.117 ns ( 70.12 % ) " "Info: Total interconnect delay = 5.117 ns ( 70.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.297 ns" { CLK_SE SREG:inst13|TEMP[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.297 ns" { CLK_SE CLK_SE~out0 SREG:inst13|TEMP[25] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.297 ns" { CLK_SE SREG:inst13|TEMP[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.297 ns" { CLK_SE CLK_SE~out0 SREG:inst13|TEMP[24] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.297 ns" { CLK_SE SREG:inst13|TEMP[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.297 ns" { CLK_SE CLK_SE~out0 SREG:inst13|TEMP[25] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "SREG.vhd" "" { Text "E:/pinlvji/SREG.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "SREG.vhd" "" { Text "E:/pinlvji/SREG.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { SREG:inst13|TEMP[25] SREG:inst13|TEMP[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.574 ns" { SREG:inst13|TEMP[25] SREG:inst13|TEMP[24] } { 0.000ns 1.265ns } { 0.000ns 0.309ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.297 ns" { CLK_SE SREG:inst13|TEMP[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.297 ns" { CLK_SE CLK_SE~out0 SREG:inst13|TEMP[24] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.297 ns" { CLK_SE SREG:inst13|TEMP[25] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.297 ns" { CLK_SE CLK_SE~out0 SREG:inst13|TEMP[25] } { 0.000ns 0.000ns 5.117ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SREG:inst13|TEMP[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { SREG:inst13|TEMP[24] } {  } {  } } } { "SREG.vhd" "" { Text "E:/pinlvji/SREG.vhd" 23 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}