frequencycount.tan.qmsg

FPGA设计频率计全套资料

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off frequencycount -c frequencycount --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off frequencycount -c frequencycount --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK_SE " "Info: Assuming node \"CLK_SE\" is an undefined clock" {  } { { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -96 -408 -240 -80 "CLK_SE" "" } { 600 864 928 616 "CLK_SE" "" } { -104 -240 -176 -88 "CLK_SE" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_SE" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "20mclk " "Info: Assuming node \"20mclk\" is an undefined clock" {  } { { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { 656 -320 -152 672 "20mclk" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "20mclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK_TEST " "Info: Assuming node \"CLK_TEST\" is an undefined clock" {  } { { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -128 -408 -240 -112 "CLK_TEST" "" } { -32 232 296 -16 "CLK_TEST" "" } { 136 240 328 152 "CLK_TEST" "" } { -136 -240 -176 -120 "CLK_TEST" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_TEST" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}