frequencycount.fnsim.qmsg

FPGA设计频率计全套资料

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 01 00:36:14 2007 " "Info: Processing started: Wed Aug 01 00:36:14 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off frequencycount -c frequencycount --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off frequencycount -c frequencycount --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pll.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll-SYN " "Info: Found design unit 1: pll-SYN" {  } { { "pll.vhd" "" { Text "E:/qautuer/pinlvji/pll.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.vhd" "" { Text "E:/qautuer/pinlvji/pll.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "STATUSCONTROL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file STATUSCONTROL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 STATUSCONTROL-MEALYMACHINE " "Info: Found design unit 1: STATUSCONTROL-MEALYMACHINE" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 STATUSCONTROL " "Info: Found entity 1: STATUSCONTROL" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "COUNTER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file COUNTER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 COUNTER-MEALYMACHINE " "Info: Found design unit 1: COUNTER-MEALYMACHINE" {  } { { "COUNTER.vhd" "" { Text "E:/qautuer/pinlvji/COUNTER.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 COUNTER " "Info: Found entity 1: COUNTER" {  } { { "COUNTER.vhd" "" { Text "E:/qautuer/pinlvji/COUNTER.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FREQUENCY10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FREQUENCY10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FREQUENCY10-DATAFLOW " "Info: Found design unit 1: FREQUENCY10-DATAFLOW" {  } { { "FREQUENCY10.vhd" "" { Text "E:/qautuer/pinlvji/FREQUENCY10.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FREQUENCY10 " "Info: Found entity 1: FREQUENCY10" {  } { { "FREQUENCY10.vhd" "" { Text "E:/qautuer/pinlvji/FREQUENCY10.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "frequencycount.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file frequencycount.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 frequencycount " "Info: Found entity 1: frequencycount" {  } { { "frequencycount.bdf" "" { Schematic "E:/qautuer/pinlvji/frequencycount.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.bdf" "" { Schematic "E:/qautuer/pinlvji/test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SREG.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SREG.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SREG-DATAFLOW " "Info: Found design unit 1: SREG-DATAFLOW" {  } { { "SREG.vhd" "" { Text "E:/qautuer/pinlvji/SREG.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SREG " "Info: Found entity 1: SREG" {  } { { "SREG.vhd" "" { Text "E:/qautuer/pinlvji/SREG.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SIGNALLTACH.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SIGNALLTACH.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SIGNALLTACH-MEALYMACHINE " "Info: Found design unit 1: SIGNALLTACH-MEALYMACHINE" {  } { { "SIGNALLTACH.vhd" "" { Text "E:/qautuer/pinlvji/SIGNALLTACH.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SIGNALLTACH " "Info: Found entity 1: SIGNALLTACH" {  } { { "SIGNALLTACH.vhd" "" { Text "E:/qautuer/pinlvji/SIGNALLTACH.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PULSEINT.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PULSEINT.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PULSEINT-MEALYMACHINE " "Info: Found design unit 1: PULSEINT-MEALYMACHINE" {  } { { "PULSEINT.vhd" "" { Text "E:/qautuer/pinlvji/PULSEINT.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PULSEINT " "Info: Found entity 1: PULSEINT" {  } { { "PULSEINT.vhd" "" { Text "E:/qautuer/pinlvji/PULSEINT.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "frequencycount " "Info: Elaborating entity \"frequencycount\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "STATUSCONTROL STATUSCONTROL:inst2 " "Info: Elaborating entity \"STATUSCONTROL\" for hierarchy \"STATUSCONTROL:inst2\"" {  } { { "frequencycount.bdf" "inst2" { Schematic "E:/qautuer/pinlvji/frequencycount.bdf" { { 88 328 536 376 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK100HZ STATUSCONTROL.vhd(125) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(125): signal \"CLK100HZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 125 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED STATUSCONTROL.vhd(126) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(126): signal \"CLKTESTED\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 126 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK10HZ STATUSCONTROL.vhd(134) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(134): signal \"CLK10HZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 134 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED STATUSCONTROL.vhd(135) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(135): signal \"CLKTESTED\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 135 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK1HZ STATUSCONTROL.vhd(143) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(143): signal \"CLK1HZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 143 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED STATUSCONTROL.vhd(144) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(144): signal \"CLKTESTED\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 144 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED10 STATUSCONTROL.vhd(152) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(152): signal \"CLKTESTED10\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 152 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK10MHZ STATUSCONTROL.vhd(153) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(153): signal \"CLK10MHZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/qautuer/pinlvji/STATUSCONTROL.vhd" 153 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}