frequencycount.fit.qmsg

来自「FPGA设计频率计全套资料」· QMSG 代码 · 共 46 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 01 15:16:27 2007 " "Info: Processing started: Wed Aug 01 15:16:27 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off frequencycount -c frequencycount " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off frequencycount -c frequencycount" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "frequencycount EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"frequencycount\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "STATUSCONTROL:inst2\|Selector11~84 Global clock " "Info: Automatically promoted signal \"STATUSCONTROL:inst2\|Selector11~84\" to use Global clock" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK_SE Global clock " "Info: Automatically promoted signal \"CLK_SE\" to use Global clock" {  } { { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -96 -408 -240 -80 "CLK_SE" "" } { 600 864 928 616 "CLK_SE" "" } { -104 -240 -176 -88 "CLK_SE" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "CLK_SE " "Info: Pin \"CLK_SE\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -96 -408 -240 -80 "CLK_SE" "" } { 600 864 928 616 "CLK_SE" "" } { -104 -240 -176 -88 "CLK_SE" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_SE" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_SE } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_SE } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "DIV2:inst10\|CLKN Global clock " "Info: Automatically promoted some destinations of signal \"DIV2:inst10\|CLKN\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DIV2:inst10\|CLKN " "Info: Destination \"DIV2:inst10\|CLKN\" may be non-global or may not use global clock" {  } { { "DIV2.vhd" "" { Text "E:/pinlvji/DIV2.vhd" 24 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "STATUSCONTROL:inst2\|Selector11~81 " "Info: Destination \"STATUSCONTROL:inst2\|Selector11~81\" may be non-global or may not use global clock" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "DIV2.vhd" "" { Text "E:/pinlvji/DIV2.vhd" 24 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREQUENCY10:inst11\|CLK_OUT Global clock " "Info: Automatically promoted some destinations of signal \"FREQUENCY10:inst11\|CLK_OUT\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY10:inst11\|CLK_OUT " "Info: Destination \"FREQUENCY10:inst11\|CLK_OUT\" may be non-global or may not use global clock" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "STATUSCONTROL:inst2\|Selector11~83 " "Info: Destination \"STATUSCONTROL:inst2\|Selector11~83\" may be non-global or may not use global clock" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "CLK_TEST Global clock " "Info: Automatically promoted some destinations of signal \"CLK_TEST\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "STATUSCONTROL:inst2\|Selector11~84 " "Info: Destination \"STATUSCONTROL:inst2\|Selector11~84\" may be non-global or may not use global clock" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "STATUSCONTROL:inst2\|Selector10~74 " "Info: Destination \"STATUSCONTROL:inst2\|Selector10~74\" may be non-global or may not use global clock" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -128 -408 -240 -112 "CLK_TEST" "" } { -32 232 296 -16 "CLK_TEST" "" } { 136 240 328 152 "CLK_TEST" "" } { -136 -240 -176 -120 "CLK_TEST" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "CLK_TEST " "Info: Pin \"CLK_TEST\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { -128 -408 -240 -112 "CLK_TEST" "" } { -32 232 296 -16 "CLK_TEST" "" } { 136 240 328 152 "CLK_TEST" "" } { -136 -240 -176 -120 "CLK_TEST" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_TEST" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_TEST } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_TEST } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREQUENCY10:inst4\|CLK_OUT Global clock " "Info: Automatically promoted some destinations of signal \"FREQUENCY10:inst4\|CLK_OUT\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY10:inst4\|CLK_OUT " "Info: Destination \"FREQUENCY10:inst4\|CLK_OUT\" may be non-global or may not use global clock" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "STATUSCONTROL:inst2\|Selector11~83 " "Info: Destination \"STATUSCONTROL:inst2\|Selector11~83\" may be non-global or may not use global clock" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREQUENCY10:inst5\|CLK_OUT Global clock " "Info: Automatically promoted some destinations of signal \"FREQUENCY10:inst5\|CLK_OUT\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY10:inst5\|CLK_OUT " "Info: Destination \"FREQUENCY10:inst5\|CLK_OUT\" may be non-global or may not use global clock" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "STATUSCONTROL:inst2\|Selector11~82 " "Info: Destination \"STATUSCONTROL:inst2\|Selector11~82\" may be non-global or may not use global clock" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREQUENCY10:inst6\|CLK_OUT Global clock " "Info: Automatically promoted some destinations of signal \"FREQUENCY10:inst6\|CLK_OUT\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK " "Info: Destination \"CLK\" may be non-global or may not use global clock" {  } { { "frequencycount.bdf" "" { Schematic "E:/pinlvji/frequencycount.bdf" { { 224 1064 1240 240 "CLK" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY10:inst6\|CLK_OUT " "Info: Destination \"FREQUENCY10:inst6\|CLK_OUT\" may be non-global or may not use global clock" {  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "STATUSCONTROL:inst2\|Selector10~75 " "Info: Destination \"STATUSCONTROL:inst2\|Selector10~75\" may be non-global or may not use global clock" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 123 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "FREQUENCY10.vhd" "" { Text "E:/pinlvji/FREQUENCY10.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}