frequencycount.map.qmsg

来自「FPGA设计频率计全套资料」· QMSG 代码 · 共 47 行 · 第 1/2 页

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK10MHZ STATUSCONTROL.vhd(153) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(153): signal \"CLK10MHZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 153 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED STATUSCONTROL.vhd(161) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(161): signal \"CLKTESTED\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 161 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK10MHZ STATUSCONTROL.vhd(162) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(162): signal \"CLK10MHZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 162 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED STATUSCONTROL.vhd(170) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(170): signal \"CLKTESTED\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 170 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK1MHZ STATUSCONTROL.vhd(171) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(171): signal \"CLK1MHZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 171 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED STATUSCONTROL.vhd(179) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(179): signal \"CLKTESTED\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 179 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK100KHZ STATUSCONTROL.vhd(180) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(180): signal \"CLK100KHZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 180 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED STATUSCONTROL.vhd(188) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(188): signal \"CLKTESTED\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 188 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK10KHZ STATUSCONTROL.vhd(189) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(189): signal \"CLK10KHZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 189 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK1KHZ STATUSCONTROL.vhd(197) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(197): signal \"CLK1KHZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 197 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED STATUSCONTROL.vhd(198) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(198): signal \"CLKTESTED\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 198 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLKTESTED STATUSCONTROL.vhd(206) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(206): signal \"CLKTESTED\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 206 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK10KHZ STATUSCONTROL.vhd(207) " "Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(207): signal \"CLK10KHZ\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 207 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DIV2 DIV2:inst10 " "Info: Elaborating entity \"DIV2\" for hierarchy \"DIV2:inst10\"" {  } { { "frequencycount.bdf" "inst10" { Schematic "E:/pinlvji/frequencycount.bdf" { { 632 -104 24 728 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FREQUENCY10 FREQUENCY10:inst1 " "Info: Elaborating entity \"FREQUENCY10\" for hierarchy \"FREQUENCY10:inst1\"" {  } { { "frequencycount.bdf" "inst1" { Schematic "E:/pinlvji/frequencycount.bdf" { { -48 296 424 48 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SIGNALLTACH SIGNALLTACH:inst3 " "Info: Elaborating entity \"SIGNALLTACH\" for hierarchy \"SIGNALLTACH:inst3\"" {  } { { "frequencycount.bdf" "inst3" { Schematic "E:/pinlvji/frequencycount.bdf" { { 384 304 432 480 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PULSEINT PULSEINT:inst14 " "Info: Elaborating entity \"PULSEINT\" for hierarchy \"PULSEINT:inst14\"" {  } { { "frequencycount.bdf" "inst14" { Schematic "E:/pinlvji/frequencycount.bdf" { { 696 448 640 824 "inst14" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|frequencycount\|STATUSCONTROL:inst2\|STATE 10 " "Info: State machine \"\|frequencycount\|STATUSCONTROL:inst2\|STATE\" contains 10 states" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 29 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|frequencycount\|STATUSCONTROL:inst2\|STATE " "Info: Selected Auto state machine encoding method for state machine \"\|frequencycount\|STATUSCONTROL:inst2\|STATE\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 29 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|frequencycount\|STATUSCONTROL:inst2\|STATE " "Info: Encoding result for state machine \"\|frequencycount\|STATUSCONTROL:inst2\|STATE\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "10 " "Info: Completed encoding using 10 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.overflowl " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.overflowl\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.overflowh " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.overflowh\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.p10s " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.p10s\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.p1s " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.p1s\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.p100ms " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.p100ms\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.p10ms " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.p10ms\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.p1ms " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.p1ms\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.f100k " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.f100k\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.f1m " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.f1m\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATUSCONTROL:inst2\|STATE.f10m " "Info: Encoded state bit \"STATUSCONTROL:inst2\|STATE.f10m\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.f10m 0000000000 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.f10m\" uses code string \"0000000000\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.f1m 0000000011 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.f1m\" uses code string \"0000000011\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.f100k 0000000101 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.f100k\" uses code string \"0000000101\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.p1ms 0000001001 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.p1ms\" uses code string \"0000001001\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.p10ms 0000010001 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.p10ms\" uses code string \"0000010001\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.p100ms 0000100001 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.p100ms\" uses code string \"0000100001\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.p1s 0001000001 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.p1s\" uses code string \"0001000001\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.p10s 0010000001 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.p10s\" uses code string \"0010000001\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.overflowh 0100000001 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.overflowh\" uses code string \"0100000001\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|frequencycount\|STATUSCONTROL:inst2\|STATE.overflowl 1000000001 " "Info: State \"\|frequencycount\|STATUSCONTROL:inst2\|STATE.overflowl\" uses code string \"1000000001\"" {  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 35 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "STATUSCONTROL.vhd" "" { Text "E:/pinlvji/STATUSCONTROL.vhd" 29 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "232 " "Info: Implemented 232 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "221 " "Info: Implemented 221 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 01 15:16:22 2007 " "Info: Processing ended: Wed Aug 01 15:16:22 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}