frequencycount.map.rpt

FPGA设计频率计全套资料

+----------------+-------+------+----------+


+------------------------------------------+
; Source assignments for FREQUENCY10:inst6 ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[3] ;
+----------------+-------+------+----------+


+------------------------------------------+
; Source assignments for FREQUENCY10:inst5 ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[3] ;
+----------------+-------+------+----------+


+------------------------------------------+
; Source assignments for FREQUENCY10:inst4 ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[3] ;
+----------------+-------+------+----------+


+-------------------------------------------+
; Source assignments for FREQUENCY10:inst11 ;
+----------------+-------+------+-----------+
; Assignment     ; Value ; From ; To        ;
+----------------+-------+------+-----------+
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[0]  ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[1]  ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[2]  ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[3]  ;
+----------------+-------+------+-----------+


+------------------------------------------+
; Source assignments for SIGNALLTACH:inst3 ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; LOCK     ;
+----------------+-------+------+----------+


+-------------------------------------------+
; Source assignments for SIGNALLTACH:inst12 ;
+----------------+-------+------+-----------+
; Assignment     ; Value ; From ; To        ;
+----------------+-------+------+-----------+
; POWER_UP_LEVEL ; Low   ; -    ; LOCK      ;
+----------------+-------+------+-----------+


+------------------------------------------+
; Source assignments for PULSEINT:inst14   ;
+----------------+-------+------+----------+
; Assignment     ; Value ; From ; To       ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; POT      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNT[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; EN       ;
+----------------+-------+------+----------+


+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: SREG:inst13 ;
+----------------+-------+---------------------------------+
; Parameter Name ; Value ; Type                            ;
+----------------+-------+---------------------------------+
; k              ; 40    ; Untyped                         ;
+----------------+-------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Aug 01 15:16:16 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off frequencycount -c frequencycount
Info: Found 2 design units, including 1 entities, in source file pll.vhd
    Info: Found design unit 1: pll-SYN
    Info: Found entity 1: pll
Info: Found 2 design units, including 1 entities, in source file STATUSCONTROL.vhd
    Info: Found design unit 1: STATUSCONTROL-MEALYMACHINE
    Info: Found entity 1: STATUSCONTROL
Info: Found 2 design units, including 1 entities, in source file COUNTER.vhd
    Info: Found design unit 1: COUNTER-MEALYMACHINE
    Info: Found entity 1: COUNTER
Info: Found 2 design units, including 1 entities, in source file FREQUENCY10.vhd
    Info: Found design unit 1: FREQUENCY10-DATAFLOW
    Info: Found entity 1: FREQUENCY10
Info: Found 1 design units, including 1 entities, in source file frequencycount.bdf
    Info: Found entity 1: frequencycount
Info: Found 1 design units, including 1 entities, in source file test.bdf
    Info: Found entity 1: test
Info: Found 2 design units, including 1 entities, in source file SREG.vhd
    Info: Found design unit 1: SREG-DATAFLOW
    Info: Found entity 1: SREG
Info: Found 2 design units, including 1 entities, in source file SIGNALLTACH.vhd
    Info: Found design unit 1: SIGNALLTACH-MEALYMACHINE
    Info: Found entity 1: SIGNALLTACH
Info: Found 2 design units, including 1 entities, in source file PULSEINT.vhd
    Info: Found design unit 1: PULSEINT-MEALYMACHINE
    Info: Found entity 1: PULSEINT
Info: Found 2 design units, including 1 entities, in source file DIV2.vhd
    Info: Found design unit 1: DIV2-DATAFLOW
    Info: Found entity 1: DIV2
Info: Elaborating entity "frequencycount" for the top level hierarchy
Info: Elaborating entity "SREG" for hierarchy "SREG:inst13"
Info: Elaborating entity "COUNTER" for hierarchy "COUNTER:inst"
Info: Elaborating entity "STATUSCONTROL" for hierarchy "STATUSCONTROL:inst2"
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(125): signal "CLK100HZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(126): signal "CLKTESTED" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(134): signal "CLK10HZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(135): signal "CLKTESTED" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(143): signal "CLK1HZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(144): signal "CLKTESTED" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(152): signal "CLKTESTED10" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(153): signal "CLK10MHZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(161): signal "CLKTESTED" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(162): signal "CLK10MHZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(170): signal "CLKTESTED" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(171): signal "CLK1MHZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(179): signal "CLKTESTED" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(180): signal "CLK100KHZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(188): signal "CLKTESTED" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(189): signal "CLK10KHZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(197): signal "CLK1KHZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(198): signal "CLKTESTED" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(206): signal "CLKTESTED" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at STATUSCONTROL.vhd(207): signal "CLK10KHZ" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "DIV2" for hierarchy "DIV2:inst10"
Info: Elaborating entity "FREQUENCY10" for hierarchy "FREQUENCY10:inst1"
Info: Elaborating entity "SIGNALLTACH" for hierarchy "SIGNALLTACH:inst3"
Info: Elaborating entity "PULSEINT" for hierarchy "PULSEINT:inst14"
Info: State machine "|frequencycount|STATUSCONTROL:inst2|STATE" contains 10 states
Info: Selected Auto state machine encoding method for state machine "|frequencycount|STATUSCONTROL:inst2|STATE"
Info: Encoding result for state machine "|frequencycount|STATUSCONTROL:inst2|STATE"
    Info: Completed encoding using 10 state bits
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.overflowl"
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.overflowh"
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.p10s"
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.p1s"
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.p100ms"
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.p10ms"
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.p1ms"
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.f100k"
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.f1m"
        Info: Encoded state bit "STATUSCONTROL:inst2|STATE.f10m"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.f10m" uses code string "0000000000"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.f1m" uses code string "0000000011"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.f100k" uses code string "0000000101"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.p1ms" uses code string "0000001001"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.p10ms" uses code string "0000010001"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.p100ms" uses code string "0000100001"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.p1s" uses code string "0001000001"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.p10s" uses code string "0010000001"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.overflowh" uses code string "0100000001"
    Info: State "|frequencycount|STATUSCONTROL:inst2|STATE.overflowl" uses code string "1000000001"
Info: Implemented 232 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 6 output pins
    Info: Implemented 221 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
    Info: Processing ended: Wed Aug 01 15:16:22 2007
    Info: Elapsed time: 00:00:07