pulseint.vhd

FPGA设计频率计全套资料

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PULSEINT IS
PORT(  CLK:IN STD_LOGIC;
       WENTRANSFER:IN STD_LOGIC;
       OVER,LOW:IN STD_LOGIC;
  
       PULSEOUT:OUT STD_LOGIC
    );
END ENTITY;

ARCHITECTURE MEALYMACHINE OF PULSEINT IS

SIGNAL EN,POT:STD_LOGIC:='0';
SIGNAL COUNT:INTEGER RANGE 0 TO 15:=0;

BEGIN

PULSEOUT<= NOT POT;

PROCESS(WENTRANSFER,COUNT)
BEGIN
IF COUNT=15 THEN
          EN<='0';
ELSIF WENTRANSFER'EVENT AND WENTRANSFER='1'  THEN
          EN<='1';     
END IF;             
END PROCESS;

PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
    IF EN='1' THEN
      IF COUNT=15 THEN
         COUNT<=0;
      ELSE
         COUNT<=COUNT+1;
      END IF;
    ELSE  
      COUNT<=0;
    END IF;
END IF;
END PROCESS;

PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
    IF COUNT=1 AND LOW='0' AND OVER='0' THEN
      POT<='1';
    ELSIF COUNT=14 THEN
      POT<='0';
    END IF;
END IF;
END PROCESS;

END;