frequencycount.qsf

FPGA设计频率计全套资料

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		frequencycount_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name TOP_LEVEL_ENTITY frequencycount
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:29:46  JULY 26, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name VECTOR_INPUT_SOURCE "E:\\qautuer\\pinlvji\\Waveform1.vwf"
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
set_global_assignment -name VHDL_FILE pll.vhd
set_global_assignment -name VHDL_FILE STATUSCONTROL.vhd
set_global_assignment -name VHDL_FILE COUNTER.vhd
set_global_assignment -name VHDL_FILE FREQUENCY10.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE FREQUENCY10.vwf
set_global_assignment -name BDF_FILE frequencycount.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE frequencycount.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE COUNT.vwf
set_global_assignment -name BDF_FILE test.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE test.vwf
set_global_assignment -name VHDL_FILE SREG.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE SREG.vwf
set_global_assignment -name VHDL_FILE SIGNALLTACH.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE LATCH.vwf
set_global_assignment -name VHDL_FILE PULSEINT.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE PULSE.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_global_assignment -name VHDL_FILE DIV2.vhd
set_location_assignment PIN_16 -to 20mclk
set_location_assignment PIN_2 -to CLK_SE
set_location_assignment PIN_3 -to CLK_TEST
set_location_assignment PIN_4 -to FRECODE[0]
set_location_assignment PIN_5 -to FRECODE[1]
set_location_assignment PIN_6 -to FRECODE[2]
set_location_assignment PIN_7 -to PULSEINT
set_location_assignment PIN_10 -to Q
set_location_assignment PIN_110 -to RESET
set_location_assignment PIN_109 -to SEL
set_location_assignment PIN_1 -to CLK