test.bdf

FPGA设计频率计全套资料

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "graphic" (version "1.3"))
(pin
	(input)
	(rect 88 144 256 160)
	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
	(text "clk" (rect 5 0 19 12)(font "Arial" ))
	(pt 168 8)
	(drawing
		(line (pt 92 12)(pt 117 12)(line_width 1))
		(line (pt 92 4)(pt 117 4)(line_width 1))
		(line (pt 121 8)(pt 168 8)(line_width 1))
		(line (pt 92 12)(pt 92 4)(line_width 1))
		(line (pt 117 4)(pt 121 8)(line_width 1))
		(line (pt 117 12)(pt 121 8)(line_width 1))
	)
	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
	(output)
	(rect 568 144 744 160)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "c0" (rect 90 0 101 12)(font "Arial" ))
	(pt 0 8)
	(drawing
		(line (pt 0 8)(pt 52 8)(line_width 1))
		(line (pt 52 4)(pt 78 4)(line_width 1))
		(line (pt 52 12)(pt 78 12)(line_width 1))
		(line (pt 52 12)(pt 52 4)(line_width 1))
		(line (pt 78 4)(pt 82 8)(line_width 1))
		(line (pt 82 8)(pt 78 12)(line_width 1))
		(line (pt 78 12)(pt 82 8)(line_width 1))
	)
)
(pin
	(output)
	(rect 568 160 744 176)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "locked" (rect 90 0 121 12)(font "Arial" ))
	(pt 0 8)
	(drawing
		(line (pt 0 8)(pt 52 8)(line_width 1))
		(line (pt 52 4)(pt 78 4)(line_width 1))
		(line (pt 52 12)(pt 78 12)(line_width 1))
		(line (pt 52 12)(pt 52 4)(line_width 1))
		(line (pt 78 4)(pt 82 8)(line_width 1))
		(line (pt 82 8)(pt 78 12)(line_width 1))
		(line (pt 78 12)(pt 82 8)(line_width 1))
	)
)
(symbol
	(rect 280 88 536 248)
	(text "pll" (rect 122 0 137 16)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 144 25 156)(font "Arial" ))
	(port
		(pt 0 64)
		(input)
		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
		(text "inclk0" (rect 4 51 35 65)(font "Arial" (font_size 8)))
		(line (pt 0 64)(pt 40 64)(line_width 1))
	)
	(port
		(pt 256 64)
		(output)
		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
		(text "c0" (rect 241 51 255 65)(font "Arial" (font_size 8)))
		(line (pt 256 64)(pt 208 64)(line_width 1))
	)
	(port
		(pt 256 80)
		(output)
		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
		(text "locked" (rect 222 67 258 81)(font "Arial" (font_size 8)))
		(line (pt 256 80)(pt 208 80)(line_width 1))
	)
	(drawing
		(text "Cyclone" (rect 213 145 254 157)(font "Arial" ))
		(text "inclk0 frequency: 20.000 MHz" (rect 50 59 197 71)(font "Arial" ))
		(text "Operation Mode: Normal" (rect 50 73 169 85)(font "Arial" ))
		(text "Clk " (rect 51 96 71 108)(font "Arial" ))
		(text "Ratio" (rect 73 96 98 108)(font "Arial" ))
		(text "Ph (dg)" (rect 100 96 135 108)(font "Arial" ))
		(text "DC (%)" (rect 135 96 171 108)(font "Arial" ))
		(text "c0" (rect 54 111 65 123)(font "Arial" ))
		(text "1/2" (rect 78 111 93 123)(font "Arial" ))
		(text "0.00" (rect 106 111 127 123)(font "Arial" ))
		(text "50.00" (rect 139 111 166 123)(font "Arial" ))
		(line (pt 0 0)(pt 257 0)(line_width 1))
		(line (pt 257 0)(pt 257 161)(line_width 1))
		(line (pt 0 161)(pt 257 161)(line_width 1))
		(line (pt 0 0)(pt 0 161)(line_width 1))
		(line (pt 48 94)(pt 168 94)(line_width 1))
		(line (pt 48 108)(pt 168 108)(line_width 1))
		(line (pt 48 123)(pt 168 123)(line_width 1))
		(line (pt 48 94)(pt 48 123)(line_width 1))
		(line (pt 70 94)(pt 70 123)(line_width 3))
		(line (pt 97 94)(pt 97 123)(line_width 3))
		(line (pt 132 94)(pt 132 123)(line_width 3))
		(line (pt 167 94)(pt 167 123)(line_width 1))
		(line (pt 40 48)(pt 208 48)(line_width 1))
		(line (pt 208 48)(pt 208 144)(line_width 1))
		(line (pt 40 144)(pt 208 144)(line_width 1))
		(line (pt 40 48)(pt 40 144)(line_width 1))
	)
)
(connector
	(pt 280 152)
	(pt 256 152)
)
(connector
	(pt 536 152)
	(pt 568 152)
)
(connector
	(pt 536 168)
	(pt 568 168)
)