div2.vhd

FPGA设计频率计全套资料

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DIV2 IS
PORT(  
       CLK:IN STD_LOGIC;
 --      COUNT1:OUT INTEGER RANGE 0 TO 9;
       CLK_OUT:OUT STD_LOGIC
       
     );
END ENTITY;

ARCHITECTURE DATAFLOW OF DIV2 IS

SIGNAL CLKN:STD_LOGIC:='0';


BEGIN

--COUNT1<=COUNT;
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
     CLKN<=NOT CLKN;
END IF;
END PROCESS;
CLK_OUT<=CLKN;
END;