frequency10.vhd

来自「FPGA设计频率计全套资料」· VHDL 代码 · 共 44 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY FREQUENCY10 IS
PORT(  
       CLK:IN STD_LOGIC;
 --      COUNT1:OUT INTEGER RANGE 0 TO 9;
       CLK_OUT:OUT STD_LOGIC
       
     );
END ENTITY;

ARCHITECTURE DATAFLOW OF FREQUENCY10 IS

SIGNAL COUNT:INTEGER RANGE 0 TO 9:=0;


BEGIN

--COUNT1<=COUNT;
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
     IF COUNT=0 THEN
   CLK_OUT<='0';
    ELSIF COUNT=5 THEN
   CLK_OUT<='1';
     END IF;
END IF;
END PROCESS;

PROCESS(CLK)
BEGIN
 IF(CLK'EVENT AND CLK='1') THEN
    IF COUNT=9 THEN
      COUNT<=0;
    ELSE
    COUNT<=COUNT+1;
    END IF;
 END IF;
END PROCESS;
END;