counter.vhd

FPGA设计频率计全套资料

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNTER IS
PORT(  CLK_COUNT:IN STD_LOGIC;
       CLK:IN STD_LOGIC;
---------------------------------
      --WEN:OUT STD_LOGIC;
      WENTRANSFER:OUT STD_LOGIC;
      --WNUM,WNUMH:OUT INTEGER RANGE 0 TO 100000;
---------------------------------       
      RESULT,RESULTH:OUT INTEGER RANGE 0 TO 100000;
       OVER,LOW:OUT STD_LOGIC
       
     );
END ENTITY;

ARCHITECTURE MEALYMACHINE OF COUNTER IS

SIGNAL NUM,NUMH:INTEGER RANGE 0 TO 100000;
SIGNAL EN:STD_LOGIC:='0';
SIGNAL ENTRANSFER:STD_LOGIC;

BEGIN

--WEN<=EN;
WENTRANSFER<=NOT ENTRANSFER;
--WNUM<=NUM;
--WNUMH<=NUMH;



PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1'  THEN
       EN<=NOT EN;
 END IF;
END PROCESS;

PROCESS(CLK_COUNT)
BEGIN
IF CLK_COUNT'EVENT AND CLK_COUNT='1' THEN
     	IF EN='1' THEN
     		IF ENTRANSFER='1' THEN
				IF NUM=100000 THEN
					LOW<='0';
					OVER<='1';
				ELSIF NUM<10000 THEN
				    LOW<='1';
				    OVER<='0';
				ELSE
					OVER<='0';
					LOW<='0';
					RESULT<=NUM;
					RESULTH<=NUMH;
				END IF;
				ENTRANSFER<='0';
			END IF;
			NUM<=0;
			NUMH<=0;
		ELSE
			ENTRANSFER<='1';
			OVER<='0';
			LOW<='0';
			IF NUM=100000 THEN
				NUM<=NUM;
			ELSE
				NUM<=NUM+1;
				IF CLK='1' THEN
				NUMH<=NUMH+1;
				ELSE
				  NULL;
				END IF;
			END IF;
		END IF;
	END IF;
END PROCESS;
END;