📄 frequencycount.tan.rpt
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; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK_SE ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; 20mclk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; CLK_TEST ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK_SE' ;
+-------+------------------------------------------------+----------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[25] ; SREG:inst13|TEMP[24] ; CLK_SE ; CLK_SE ; None ; None ; 1.574 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[20] ; SREG:inst13|TEMP[19] ; CLK_SE ; CLK_SE ; None ; None ; 1.567 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[0] ; SREG:inst13|Q ; CLK_SE ; CLK_SE ; None ; None ; 1.555 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[10] ; SREG:inst13|TEMP[9] ; CLK_SE ; CLK_SE ; None ; None ; 1.471 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[35] ; SREG:inst13|TEMP[34] ; CLK_SE ; CLK_SE ; None ; None ; 1.447 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[16] ; SREG:inst13|TEMP[15] ; CLK_SE ; CLK_SE ; None ; None ; 1.337 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[18] ; SREG:inst13|TEMP[17] ; CLK_SE ; CLK_SE ; None ; None ; 1.335 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[38] ; SREG:inst13|TEMP[37] ; CLK_SE ; CLK_SE ; None ; None ; 1.275 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[28] ; SREG:inst13|TEMP[27] ; CLK_SE ; CLK_SE ; None ; None ; 1.121 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[33] ; SREG:inst13|TEMP[32] ; CLK_SE ; CLK_SE ; None ; None ; 1.117 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[12] ; SREG:inst13|TEMP[11] ; CLK_SE ; CLK_SE ; None ; None ; 1.114 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[13] ; SREG:inst13|TEMP[12] ; CLK_SE ; CLK_SE ; None ; None ; 1.114 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[2] ; SREG:inst13|TEMP[1] ; CLK_SE ; CLK_SE ; None ; None ; 1.112 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[19] ; SREG:inst13|TEMP[18] ; CLK_SE ; CLK_SE ; None ; None ; 1.027 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[7] ; SREG:inst13|TEMP[6] ; CLK_SE ; CLK_SE ; None ; None ; 1.026 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[34] ; SREG:inst13|TEMP[33] ; CLK_SE ; CLK_SE ; None ; None ; 1.026 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[29] ; SREG:inst13|TEMP[28] ; CLK_SE ; CLK_SE ; None ; None ; 1.025 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[31] ; SREG:inst13|TEMP[30] ; CLK_SE ; CLK_SE ; None ; None ; 1.025 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[15] ; SREG:inst13|TEMP[14] ; CLK_SE ; CLK_SE ; None ; None ; 1.024 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[17] ; SREG:inst13|TEMP[16] ; CLK_SE ; CLK_SE ; None ; None ; 1.024 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[24] ; SREG:inst13|TEMP[23] ; CLK_SE ; CLK_SE ; None ; None ; 1.023 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[14] ; SREG:inst13|TEMP[13] ; CLK_SE ; CLK_SE ; None ; None ; 1.022 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[11] ; SREG:inst13|TEMP[10] ; CLK_SE ; CLK_SE ; None ; None ; 1.021 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[30] ; SREG:inst13|TEMP[29] ; CLK_SE ; CLK_SE ; None ; None ; 1.021 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[32] ; SREG:inst13|TEMP[31] ; CLK_SE ; CLK_SE ; None ; None ; 1.021 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[8] ; SREG:inst13|TEMP[7] ; CLK_SE ; CLK_SE ; None ; None ; 1.020 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[9] ; SREG:inst13|TEMP[8] ; CLK_SE ; CLK_SE ; None ; None ; 1.020 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SREG:inst13|TEMP[21] ; SREG:inst13|TEMP[20] ; CLK_SE ; CLK_SE ; None ; None ; 1.020 ns ;
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