📄 nclight.txt
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY nclight IS
Port(clk : in std_logic;
ra,rb,ya,yb,ga,gb : out std_logic );
END nclight;
Architecture a of nclight is
type state is (S0,S1,S2,S3);
signal presentstate,nextstate : state;
signal tmp1,tmp2 : integer range 0 to 40;
signal timeout1,timeout2: std_logic;
signal q: std_logic_vector(21 downto 0);
signal sec: std_logic;
Begin
----get 1 hz clock pulse
process(clk)
begin
if clk'event and clk='1' then q<=q+1; end if;
sec<=q(21); --get 1 hz clock pulse
end process;
timing: process(sec)
begin
if sec'event and sec='1' then
if tmp1=39 then timeout1<='1'; timeout2<='0'; tmp1<=0; else
if timeout1='1' then
if tmp2=4 then timeout2<='1'; timeout1<='0'; tmp2<=0;
else tmp2<=tmp2+1; end if;
else tmp1<=tmp1+1; end if;
end if;
end if;
end process;
changestate: process(presentstate)
Begin
case presentstate is
when S0 => if timeout1='0' then
nextstate<=s0;
ra<='0'; ya<='0'; ga<='1';
rb<='1'; yb<='0'; gb<='0';
else nextstate<=s1; end if;
when S1 => if timeout2='0' then
nextstate<=s1;
ra<='0'; ya<='1'; ga<='0';
rb<='1'; yb<='0'; gb<='0';
else nextstate<=s2; end if;
when S2 => if timeout1='0' then
nextstate<=s2;
ra<='1'; ya<='0'; ga<=‘1';
rb<='0'; yb<='0'; gb<='1';
else nextstate<=s3; end if;
when S3 => if timeout2='0' then
nextstate<=s3;
ra<='1'; ya<='0'; ga<='0';
rb<='0'; yb<='1'; gb<='0';
else nextstate<=s0; end if;
when others => nextstate<=s0;
timeout1<='0'; timeout2<='0';
end case;
end process;
end a;
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