keyboardvhdl.tan.rpt

CPLD的小程序集合

    Info: + Longest register to register delay is 6.242 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N4; Fanout = 2; REG Node = 'shiftRegSig2[6]'
        Info: 2: + IC(0.908 ns) + CELL(0.914 ns) = 1.822 ns; Loc. = LC_X5_Y2_N7; Fanout = 1; COMB Node = 'Equal0~65'
        Info: 3: + IC(0.718 ns) + CELL(0.740 ns) = 3.280 ns; Loc. = LC_X5_Y2_N5; Fanout = 8; COMB Node = 'Equal0~66'
        Info: 4: + IC(1.719 ns) + CELL(1.243 ns) = 6.242 ns; Loc. = LC_X7_Y2_N9; Fanout = 1; REG Node = 'WaitReg[2]'
        Info: Total cell delay = 2.897 ns ( 46.41 % )
        Info: Total interconnect delay = 3.345 ns ( 53.59 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 11.902 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv[3]'
            Info: 3: + IC(3.220 ns) + CELL(1.294 ns) = 8.238 ns; Loc. = LC_X2_Y3_N4; Fanout = 29; REG Node = 'KCI'
            Info: 4: + IC(2.746 ns) + CELL(0.918 ns) = 11.902 ns; Loc. = LC_X7_Y2_N9; Fanout = 1; REG Node = 'WaitReg[2]'
            Info: Total cell delay = 4.669 ns ( 39.23 % )
            Info: Total interconnect delay = 7.233 ns ( 60.77 % )
        Info: - Longest clock path from clock "CLK" to source register is 11.902 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv[3]'
            Info: 3: + IC(3.220 ns) + CELL(1.294 ns) = 8.238 ns; Loc. = LC_X2_Y3_N4; Fanout = 29; REG Node = 'KCI'
            Info: 4: + IC(2.746 ns) + CELL(0.918 ns) = 11.902 ns; Loc. = LC_X5_Y2_N4; Fanout = 2; REG Node = 'shiftRegSig2[6]'
            Info: Total cell delay = 4.669 ns ( 39.23 % )
            Info: Total interconnect delay = 7.233 ns ( 60.77 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "CLK" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "KDI" and destination pin or register "shiftRegSig1[10]" for clock "CLK" (Hold time is 2.375 ns)
    Info: + Largest clock skew is 4.040 ns
        Info: + Longest clock path from clock "CLK" to destination register is 11.902 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv[3]'
            Info: 3: + IC(3.220 ns) + CELL(1.294 ns) = 8.238 ns; Loc. = LC_X2_Y3_N4; Fanout = 29; REG Node = 'KCI'
            Info: 4: + IC(2.746 ns) + CELL(0.918 ns) = 11.902 ns; Loc. = LC_X6_Y1_N6; Fanout = 1; REG Node = 'shiftRegSig1[10]'
            Info: Total cell delay = 4.669 ns ( 39.23 % )
            Info: Total interconnect delay = 7.233 ns ( 60.77 % )
        Info: - Shortest clock path from clock "CLK" to source register is 7.862 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv[3]'
            Info: 3: + IC(3.220 ns) + CELL(0.918 ns) = 7.862 ns; Loc. = LC_X6_Y1_N2; Fanout = 1; REG Node = 'KDI'
            Info: Total cell delay = 3.375 ns ( 42.93 % )
            Info: Total interconnect delay = 4.487 ns ( 57.07 % )
    Info: - Micro clock to output delay of source is 0.376 ns
    Info: - Shortest register to register delay is 1.510 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y1_N2; Fanout = 1; REG Node = 'KDI'
        Info: 2: + IC(0.919 ns) + CELL(0.591 ns) = 1.510 ns; Loc. = LC_X6_Y1_N6; Fanout = 1; REG Node = 'shiftRegSig1[10]'
        Info: Total cell delay = 0.591 ns ( 39.14 % )
        Info: Total interconnect delay = 0.919 ns ( 60.86 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "DFF1" (data pin = "KD", clock pin = "CLK") is -0.907 ns
    Info: + Longest pin to register delay is 6.622 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 1; PIN Node = 'KD'
        Info: 2: + IC(5.210 ns) + CELL(0.280 ns) = 6.622 ns; Loc. = LC_X6_Y1_N9; Fanout = 1; REG Node = 'DFF1'
        Info: Total cell delay = 1.412 ns ( 21.32 % )
        Info: Total interconnect delay = 5.210 ns ( 78.68 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 7.862 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv[3]'
        Info: 3: + IC(3.220 ns) + CELL(0.918 ns) = 7.862 ns; Loc. = LC_X6_Y1_N9; Fanout = 1; REG Node = 'DFF1'
        Info: Total cell delay = 3.375 ns ( 42.93 % )
        Info: Total interconnect delay = 4.487 ns ( 57.07 % )
Info: tco from clock "CLK" to destination pin "sseg[5]" through register "WaitReg[3]" is 26.894 ns
    Info: + Longest clock path from clock "CLK" to source register is 11.902 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv[3]'
        Info: 3: + IC(3.220 ns) + CELL(1.294 ns) = 8.238 ns; Loc. = LC_X2_Y3_N4; Fanout = 29; REG Node = 'KCI'
        Info: 4: + IC(2.746 ns) + CELL(0.918 ns) = 11.902 ns; Loc. = LC_X6_Y2_N4; Fanout = 2; REG Node = 'WaitReg[3]'
        Info: Total cell delay = 4.669 ns ( 39.23 % )
        Info: Total interconnect delay = 7.233 ns ( 60.77 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 14.616 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N4; Fanout = 2; REG Node = 'WaitReg[3]'
        Info: 2: + IC(1.300 ns) + CELL(0.200 ns) = 1.500 ns; Loc. = LC_X5_Y2_N9; Fanout = 15; COMB Node = 'MUXOUT[3]~39'
        Info: 3: + IC(3.151 ns) + CELL(0.740 ns) = 5.391 ns; Loc. = LC_X5_Y3_N3; Fanout = 4; COMB Node = 'Equal16~246'
        Info: 4: + IC(1.732 ns) + CELL(0.511 ns) = 7.634 ns; Loc. = LC_X7_Y3_N2; Fanout = 1; COMB Node = 'sseg~1648'
        Info: 5: + IC(1.754 ns) + CELL(0.914 ns) = 10.302 ns; Loc. = LC_X6_Y2_N0; Fanout = 1; COMB Node = 'sseg~1650'
        Info: 6: + IC(1.992 ns) + CELL(2.322 ns) = 14.616 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'sseg[5]'
        Info: Total cell delay = 4.687 ns ( 32.07 % )
        Info: Total interconnect delay = 9.929 ns ( 67.93 % )
Info: th for register "DFF2" (data pin = "KC", clock pin = "CLK") is 2.364 ns
    Info: + Longest clock path from clock "CLK" to destination register is 7.862 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv[3]'
        Info: 3: + IC(3.220 ns) + CELL(0.918 ns) = 7.862 ns; Loc. = LC_X2_Y3_N2; Fanout = 1; REG Node = 'DFF2'
        Info: Total cell delay = 3.375 ns ( 42.93 % )
        Info: Total interconnect delay = 4.487 ns ( 57.07 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.719 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'KC'
        Info: 2: + IC(4.307 ns) + CELL(0.280 ns) = 5.719 ns; Loc. = LC_X2_Y3_N2; Fanout = 1; REG Node = 'DFF2'
        Info: Total cell delay = 1.412 ns ( 24.69 % )
        Info: Total interconnect delay = 4.307 ns ( 75.31 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Thu Feb 12 00:00:48 2009
    Info: Elapsed time: 00:00:02