📄 rs232.rpt
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-- Node name is '|RS232TTX:10|:18' = '|RS232TTX:10|DIN_LATCH2'
-- Equation name is '_LC2_F35', type is buried
_LC2_F35 = DFFE( _LC8_F33, _LC2_F30, VCC, VCC, VCC);
-- Node name is '|RS232TTX:10|:17' = '|RS232TTX:10|DIN_LATCH3'
-- Equation name is '_LC3_F35', type is buried
_LC3_F35 = DFFE( _LC5_F33, _LC2_F30, VCC, VCC, VCC);
-- Node name is '|RS232TTX:10|:16' = '|RS232TTX:10|DIN_LATCH4'
-- Equation name is '_LC6_F20', type is buried
_LC6_F20 = DFFE( _LC2_F26, _LC2_F30, VCC, VCC, VCC);
-- Node name is '|RS232TTX:10|:15' = '|RS232TTX:10|DIN_LATCH5'
-- Equation name is '_LC7_F20', type is buried
_LC7_F20 = DFFE( _LC1_F33, _LC2_F30, VCC, VCC, VCC);
-- Node name is '|RS232TTX:10|:14' = '|RS232TTX:10|DIN_LATCH6'
-- Equation name is '_LC5_F35', type is buried
_LC5_F35 = DFFE( _LC4_F33, _LC2_F30, VCC, VCC, VCC);
-- Node name is '|RS232TTX:10|:13' = '|RS232TTX:10|DIN_LATCH7'
-- Equation name is '_LC2_F20', type is buried
_LC2_F20 = DFFE( _LC1_F21, _LC2_F30, VCC, VCC, VCC);
-- Node name is '|RS232TTX:10|LPM_ADD_SUB:356|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_F28', type is buried
_LC8_F28 = LCELL( _EQ062);
_EQ062 = _LC4_F28 & _LC5_F28;
-- Node name is '|RS232TTX:10|LPM_ADD_SUB:356|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_F34', type is buried
_LC8_F34 = LCELL( _EQ063);
_EQ063 = _LC4_F34 & _LC8_F28;
-- Node name is '|RS232TTX:10|LPM_ADD_SUB:356|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_F34', type is buried
_LC6_F34 = LCELL( _EQ064);
_EQ064 = _LC3_F34 & _LC4_F34 & _LC8_F28;
-- Node name is '|RS232TTX:10|:238' = '|RS232TTX:10|SCIT_V0'
-- Equation name is '_LC5_F28', type is buried
_LC5_F28 = DFFE( _EQ065, _LC1_D15, VCC, VCC, VCC);
_EQ065 = _LC2_F28 & !_LC5_F28;
-- Node name is '|RS232TTX:10|:237' = '|RS232TTX:10|SCIT_V1'
-- Equation name is '_LC4_F28', type is buried
_LC4_F28 = DFFE( _EQ066, _LC1_D15, VCC, VCC, VCC);
_EQ066 = _LC2_F28 & !_LC4_F28 & _LC5_F28
# _LC2_F28 & _LC4_F28 & !_LC5_F28;
-- Node name is '|RS232TTX:10|:236' = '|RS232TTX:10|SCIT_V2'
-- Equation name is '_LC4_F34', type is buried
_LC4_F34 = DFFE( _EQ067, _LC1_D15, VCC, VCC, VCC);
_EQ067 = _LC2_F28 & _LC4_F34 & !_LC8_F28
# _LC2_F28 & !_LC4_F34 & _LC8_F28
# _LC7_F34;
-- Node name is '|RS232TTX:10|:235' = '|RS232TTX:10|SCIT_V3'
-- Equation name is '_LC3_F34', type is buried
_LC3_F34 = DFFE( _EQ068, _LC1_D15, VCC, VCC, VCC);
_EQ068 = _LC2_F28 & _LC3_F34 & !_LC8_F34
# _LC2_F28 & !_LC3_F34 & _LC8_F34
# _LC7_F34;
-- Node name is '|RS232TTX:10|:234' = '|RS232TTX:10|SCIT_V4'
-- Equation name is '_LC5_F34', type is buried
_LC5_F34 = DFFE( _EQ069, _LC1_D15, VCC, VCC, VCC);
_EQ069 = _LC2_F28 & _LC5_F34 & !_LC6_F34
# _LC2_F28 & !_LC5_F34 & _LC6_F34
# _LC7_F34;
-- Node name is '|RS232TTX:10|:233' = '|RS232TTX:10|SCIT_V5'
-- Equation name is '_LC1_F34', type is buried
_LC1_F34 = DFFE( _EQ070, _LC1_D15, VCC, VCC, VCC);
_EQ070 = _LC1_F34 & !_LC5_F34
# _LC1_F34 & !_LC6_F34
# !_LC1_F34 & _LC2_F34 & _LC5_F34 & _LC6_F34;
-- Node name is '|RS232TTX:10|:22' = '|RS232TTX:10|TDEMPTY_S'
-- Equation name is '_LC1_F28', type is buried
_LC1_F28 = DFFE( _EQ071, _LC1_D15, _LC2_F30, VCC, VCC);
_EQ071 = _LC1_F28
# !_LC3_F28 & _LC7_F28 & _LC8_F28;
-- Node name is '|RS232TTX:10|:21' = '|RS232TTX:10|TXDF'
-- Equation name is '_LC3_F28', type is buried
_LC3_F28 = DFFE( _EQ072, _LC1_D15, _LC2_F30, VCC, VCC);
_EQ072 = _LC3_F28
# _LC1_F34 & _LC2_F34 & _LC8_F28;
-- Node name is '|RS232TTX:10|~202~1'
-- Equation name is '_LC7_F28', type is buried
-- synthesized logic cell
_LC7_F28 = LCELL( _EQ073);
_EQ073 = _LC1_F34 & _LC2_F34;
-- Node name is '|RS232TTX:10|:258'
-- Equation name is '_LC2_F28', type is buried
_LC2_F28 = LCELL( _EQ074);
_EQ074 = _LC1_F34
# _LC2_F34;
-- Node name is '|RS232TTX:10|:260'
-- Equation name is '_LC2_F34', type is buried
_LC2_F34 = LCELL( _EQ075);
_EQ075 = _LC3_F34 & _LC4_F34 & _LC5_F34;
-- Node name is '|RS232TTX:10|:379'
-- Equation name is '_LC7_F34', type is buried
_LC7_F34 = LCELL( _EQ076);
_EQ076 = !_LC1_F28 & !_LC2_F28 & _LC2_F30;
-- Node name is '|RS232TTX:10|~727~1'
-- Equation name is '_LC4_F35', type is buried
-- synthesized logic cell
_LC4_F35 = LCELL( _EQ077);
_EQ077 = _LC2_F35 & !_LC4_F34
# _LC3_F35 & _LC4_F34;
-- Node name is '|RS232TTX:10|~727~2'
-- Equation name is '_LC1_F35', type is buried
-- synthesized logic cell
_LC1_F35 = LCELL( _EQ078);
_EQ078 = _LC4_F35 & !_LC5_F34
# !_LC4_F34 & _LC5_F34 & _LC5_F35;
-- Node name is '|RS232TTX:10|~727~3'
-- Equation name is '_LC5_F20', type is buried
-- synthesized logic cell
_LC5_F20 = LCELL( _EQ079);
_EQ079 = _LC3_F20 & !_LC4_F34 & !_LC5_F34
# _LC4_F20 & _LC4_F34 & !_LC5_F34;
-- Node name is '|RS232TTX:10|~727~4'
-- Equation name is '_LC8_F20', type is buried
-- synthesized logic cell
_LC8_F20 = LCELL( _EQ080);
_EQ080 = !_LC4_F34 & _LC5_F34 & _LC6_F20
# _LC4_F34 & _LC5_F34 & _LC7_F20;
-- Node name is '|RS232TTX:10|~727~5'
-- Equation name is '_LC1_F20', type is buried
-- synthesized logic cell
_LC1_F20 = LCELL( _EQ081);
_EQ081 = _LC1_F35 & _LC3_F34
# !_LC3_F34 & _LC5_F20
# !_LC3_F34 & _LC8_F20;
-- Node name is '|RS232TTX:10|:727'
-- Equation name is '_LC6_F28', type is buried
_LC6_F28 = LCELL( _EQ082);
_EQ082 = _LC1_F20 & _LC1_F34
# !_LC1_F34 & !_LC2_F34
# _LC1_F34 & _LC2_F20 & _LC2_F34;
Project Information f:\ksprogramme\13\serial\rs232.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:05
Database Builder 00:00:01
Logic Synthesizer 00:00:02
Partitioner 00:00:02
Fitter 00:00:07
Timing SNF Extractor 00:00:01
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:19
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,985K
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