📄 control.rpt
字号:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 11/ 48( 22%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\ksprogramme\serial\control.rpt
control
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 15 CLK
Device-Specific Information: e:\ksprogramme\serial\control.rpt
control
** EQUATIONS **
CLK : INPUT;
RDFULL : INPUT;
TDEMPTY : INPUT;
-- Node name is 'CLK_OUT'
-- Equation name is 'CLK_OUT', type is output
CLK_OUT = _LC6_B8;
-- Node name is ':23' = 'COUNT0'
-- Equation name is 'COUNT0', location is LC3_B11, type is buried.
COUNT0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !COUNT0 & _LC8_B4;
-- Node name is ':22' = 'COUNT1'
-- Equation name is 'COUNT1', location is LC5_B8, type is buried.
COUNT1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = COUNT0 & !COUNT1 & _LC8_B4
# !COUNT0 & COUNT1 & _LC8_B4;
-- Node name is ':21' = 'COUNT2'
-- Equation name is 'COUNT2', location is LC7_B11, type is buried.
COUNT2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !COUNT0 & COUNT2 & _LC8_B4
# !COUNT1 & COUNT2 & _LC8_B4
# COUNT0 & COUNT1 & !COUNT2 & _LC8_B4;
-- Node name is ':20' = 'COUNT3'
-- Equation name is 'COUNT3', location is LC5_B11, type is buried.
COUNT3 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = COUNT3 & !_LC4_B11 & _LC8_B4
# !COUNT3 & _LC4_B11 & _LC8_B4;
-- Node name is ':19' = 'COUNT4'
-- Equation name is 'COUNT4', location is LC6_B11, type is buried.
COUNT4 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = !COUNT3 & COUNT4 & _LC8_B4
# COUNT4 & !_LC4_B11 & _LC8_B4
# COUNT3 & !COUNT4 & _LC4_B11 & _LC8_B4;
-- Node name is ':18' = 'COUNT5'
-- Equation name is 'COUNT5', location is LC2_B11, type is buried.
COUNT5 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = COUNT5 & _LC8_B4 & !_LC8_B11
# !COUNT5 & _LC8_B4 & _LC8_B11;
-- Node name is ':17' = 'COUNT6'
-- Equation name is 'COUNT6', location is LC2_B4, type is buried.
COUNT6 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = !COUNT5 & COUNT6 & _LC8_B4
# COUNT6 & _LC8_B4 & !_LC8_B11
# COUNT5 & !COUNT6 & _LC8_B4 & _LC8_B11;
-- Node name is ':16' = 'COUNT7'
-- Equation name is 'COUNT7', location is LC7_B4, type is buried.
COUNT7 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = COUNT7 & !_LC1_B4 & _LC8_B4
# !COUNT7 & _LC1_B4 & _LC8_B4;
-- Node name is ':15' = 'COUNT8'
-- Equation name is 'COUNT8', location is LC6_B4, type is buried.
COUNT8 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = !COUNT7 & COUNT8 & _LC8_B4
# COUNT8 & !_LC1_B4 & _LC8_B4
# COUNT7 & !COUNT8 & _LC1_B4 & _LC8_B4;
-- Node name is ':14' = 'COUNT9'
-- Equation name is 'COUNT9', location is LC4_B4, type is buried.
COUNT9 = DFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = !COUNT8 & COUNT9 & _LC8_B4
# COUNT9 & !_LC3_B4 & _LC8_B4
# COUNT8 & !COUNT9 & _LC3_B4 & _LC8_B4;
-- Node name is 'RD'
-- Equation name is 'RD', type is output
RD = _LC3_B19;
-- Node name is ':13' = 'S0'
-- Equation name is 'S0', location is LC2_B19, type is buried.
S0 = DFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = _LC1_B19 & !S0;
-- Node name is ':12' = 'S1~41'
-- Equation name is 'S1~41', location is LC4_B19, type is buried.
S1~41 = DFFE( _EQ012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = _LC1_B19 & S0 & !S1~41
# _LC1_B19 & !S0 & S1~41;
-- Node name is 'WR'
-- Equation name is 'WR', type is output
WR = _LC5_B19;
-- Node name is '|LPM_ADD_SUB:350|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ013);
_EQ013 = COUNT0 & COUNT1 & COUNT2;
-- Node name is '|LPM_ADD_SUB:350|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = LCELL( _EQ014);
_EQ014 = COUNT3 & COUNT4 & _LC4_B11;
-- Node name is '|LPM_ADD_SUB:350|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = LCELL( _EQ015);
_EQ015 = COUNT5 & COUNT6 & _LC8_B11;
-- Node name is '|LPM_ADD_SUB:350|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = LCELL( _EQ016);
_EQ016 = COUNT7 & _LC1_B4;
-- Node name is ':4'
-- Equation name is '_LC3_B19', type is buried
_LC3_B19 = DFFE( _EQ017, GLOBAL( CLK), VCC, VCC, VCC);
_EQ017 = _LC3_B19 & !S0
# _LC3_B19 & S1~41
# !RDFULL;
-- Node name is ':6'
-- Equation name is '_LC5_B19', type is buried
_LC5_B19 = DFFE( _EQ018, GLOBAL( CLK), VCC, VCC, VCC);
_EQ018 = _LC5_B19 & !S0
# _LC5_B19 & S1~41
# !_LC1_B19;
-- Node name is ':8'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = DFFE( _EQ019, GLOBAL( CLK), VCC, VCC, VCC);
_EQ019 = COUNT0 & !COUNT1 & _LC1_B11 & _LC5_B4;
-- Node name is ':134'
-- Equation name is '_LC1_B19', type is buried
_LC1_B19 = LCELL( _EQ020);
_EQ020 = RDFULL & TDEMPTY;
-- Node name is ':273'
-- Equation name is '_LC8_B4', type is buried
_LC8_B4 = LCELL( _EQ021);
_EQ021 = !COUNT7 & _LC4_B8
# !COUNT8
# !COUNT9;
-- Node name is ':288'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ022);
_EQ022 = !COUNT6
# !COUNT0 & !COUNT1 & _LC1_B11;
-- Node name is '~290~1'
-- Equation name is '~290~1', location is LC1_B11, type is buried.
-- synthesized logic cell
_LC1_B11 = LCELL( _EQ023);
_EQ023 = !COUNT2 & !COUNT3 & !COUNT4 & !COUNT5;
-- Node name is '~578~1'
-- Equation name is '~578~1', location is LC5_B4, type is buried.
-- synthesized logic cell
_LC5_B4 = LCELL( _EQ024);
_EQ024 = COUNT6 & !COUNT7 & COUNT8 & COUNT9;
Project Information e:\ksprogramme\serial\control.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,885K
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