fenpin.vhd

来自「异步串口通信口在FPGA实现」· VHDL 代码 · 共 36 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY FENPIN IS 
    PORT(CLK:IN STD_LOGIC;
         CLK_OUT:OUT STD_LOGIC);
END FENPIN;
ARCHITECTURE CHU OF FENPIN IS
SIGNAL COUNT:	STD_LOGIC_VECTOR(10 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
  IF COUNT<5 THEN 
    COUNT<=COUNT+"00000000001";
  ELSE 
    COUNT<="00000000000";
  END IF;
END IF; 
END PROCESS;

PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
	IF COUNT>=0 AND COUNT<3 THEN 
	   CLK_OUT<='0';
	ELSE 
       CLK_OUT<='1';
    END IF;
END IF;
END PROCESS;
END CHU;