control.vhd

异步串口通信口在FPGA实现

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CONTROL IS
	PORT(TDEMPTY,RDFULL,CLK:IN STD_LOGIC;
		 RD,WR:OUT STD_LOGIC;
                 CLK_OUT:OUT STD_LOGIC
);
END CONTROL;

ARCHITECTURE RTL OF CONTROL IS
SIGNAL S,S1:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL CLK1:STD_LOGIC;
SIGNAL COUNT:STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
PROCESS(RDFULL,CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
	IF(RDFULL='1')THEN
        S1<=S1+1;
        IF(S="01")THEN
           RD<='0';
        END IF;
    ELSE
        RD<='1';
	END IF;
END IF;
END PROCESS;

PROCESS(TDEMPTY,CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
	IF(TDEMPTY='1' AND RDFULL='1')THEN
       S<=S+1;  
       IF(S="01")THEN
         WR<='0';
       END IF;
    ELSE
       S<="00";  
       WR<='1';
	END IF;
END IF;
END PROCESS;

PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
	IF COUNT<833 THEN
		COUNT<=COUNT+1;
	ELSE
		COUNT<="0000000000";
	END IF;
END IF;
END PROCESS;

PROCESS(COUNT,CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF COUNT=833 THEN
CLK_OUT<='1';
CLK1<='1';
ELSE
CLK1<='0';
CLK_OUT<='0';
END IF;
END IF;
END PROCESS;

END RTL;