rs232rtx.vhd

异步串口通信口在FPGA实现

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RS232RTX IS
	PORT(CLKS,RXD,RD:IN STD_LOGIC;
		 RDFULL:OUT STD_LOGIC;
		 DATA:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END RS232RTX;
ARCHITECTURE RTL OF RS232RTX IS
SIGNAL SCIR:		STD_ULOGIC_VECTOR(5 DOWNTO 0);--RECIEVE COUNTER
SIGNAL SH_R:		STD_ULOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SL_R:		STD_ULOGIC_VECTOR(1 DOWNTO 0);
SIGNAL D_FB:		STD_ULOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DO_LATCH:	STD_ULOGIC_VECTOR(7 DOWNTO 0);--OUTPUT LATCH
SIGNAL RXDF:	STD_ULOGIC;--REC TRANS STATUS BIT
SIGNAL RDFULL_S:	STD_ULOGIC:='0';--RECIEVE FULL
BEGIN
	SH_R<=SCIR(5 DOWNTO 2);
	SL_R<=SCIR(1 DOWNTO 0);
        RDFULL<=RDFULL_S;


PROCESS(CLKS,RD)--FULL AND LATCH
BEGIN
	IF(RD='0')THEN
		RDFULL_S<='0';
	ELSIF(CLKS'EVENT AND CLKS='1')THEN
		IF((RXDF='1')AND(SH_R="1111")AND(SL_R="11"))THEN
			DO_LATCH<=D_FB;
			RDFULL_S<='1';
		END IF;
	END IF;
END PROCESS;

PROCESS(CLKS)
BEGIN
	IF(CLKS'EVENT AND CLKS='1')THEN
		IF(RXD='0')THEN
			RXDF<='1';
		ELSIF((RXDF='1')AND(SH_R="1111")AND(SL_R="11"))THEN
			RXDF<='0';
		END IF;
	END IF;
END PROCESS;

PROCESS(RD)
VARIABLE DO_LATCH_V:STD_ULOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	DO_LATCH_V:=DO_LATCH;
	IF(RD='0')THEN
                DATA<=TO_STDLOGICVECTOR(DO_LATCH_V);
	END IF;
END PROCESS;

PROCESS(CLKS)
VARIABLE SCIR_V:INTEGER RANGE 0 TO 63;
VARIABLE SCIR_S:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
	
	IF(CLKS'EVENT AND CLKS='1')THEN
		IF((SCIR_V<=27)AND(RXD='0'))THEN
			SCIR_V:=28;
		ELSIF((SCIR_V<=27)AND(RXD='1'))THEN
			SCIR_V:=0;
		ELSE
			SCIR_V:=SCIR_V+1;
		END IF;
	END IF;
SCIR_S:=CONV_STD_LOGIC_VECTOR(SCIR_V,6);
SCIR<=TO_STDULOGICVECTOR(SCIR_S);
END PROCESS;

PROCESS(CLKS)
BEGIN
	IF(CLKS'EVENT AND CLKS='0')THEN
		IF((SH_R>="1000")AND(SH_R<="1111")AND(SL_R="01"))THEN
			D_FB(7)<=RXD;
			FOR I IN 0 TO 6 LOOP
			D_FB(I)<=D_FB(I+1);
			END LOOP;
		END IF;
	END IF;
 END PROCESS;

END RTL;