rs232ttx.vhd

异步串口通信口在FPGA实现

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RS232TTX IS
	PORT(CLKS,WR:IN STD_LOGIC;
		 TXD,TDEMPTY:OUT STD_LOGIC;
		 DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0));
END RS232TTX;
ARCHITECTURE RTL OF RS232TTX IS

SIGNAL SH_T:		STD_ULOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SL_T:		STD_ULOGIC_VECTOR(1 DOWNTO 0);
SIGNAL SCIT:		STD_ULOGIC_VECTOR(5 DOWNTO 0);--TRANS COUNTER
SIGNAL DIN_LATCH:	STD_ULOGIC_VECTOR(7 DOWNTO 0);--INPUT LATCH
SIGNAL TXDF:	STD_ULOGIC;--REC TRANS STATUS BIT
SIGNAL TDEMPTY_S:	STD_ULOGIC:='1';--TRANS EMPTY
BEGIN
SH_T<=SCIT(5 DOWNTO 2);
SL_T<=SCIT(1 DOWNTO 0);
TDEMPTY<=TDEMPTY_S;


PROCESS(WR)
VARIABLE DATA_V:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	IF(WR'EVENT AND WR='1')THEN
		
			DATA_V:=DATA;---why?
			DIN_LATCH<=TO_STDULOGICVECTOR(DATA_V);
	END IF;
END PROCESS;

PROCESS(WR,CLKS)
BEGIN
	IF(WR='0')THEN
		TXDF<='0';
		TDEMPTY_S<='0';
	ELSIF(CLKS'EVENT AND CLKS='1')THEN
		IF(((TXDF='0')AND(SH_T="1111")AND(SL_T="11")))THEN
			TDEMPTY_S<='1';
			TXDF<='1';
		END IF;
	END IF;
END PROCESS;

PROCESS(CLKS)
VARIABLE SCIT_V:INTEGER RANGE 0 TO 63;
VARIABLE SCIT_S:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
	IF(CLKS'EVENT AND CLKS='1')THEN
		IF(SCIT_V<=27)THEN
			IF(TDEMPTY_S='0'AND WR='1')THEN
				SCIT_V:=28;
			ELSE
				SCIT_V:=0;
			END IF;
		ELSE
			SCIT_V:=SCIT_V+1;
		END IF;
	END IF;
SCIT_S:=CONV_STD_LOGIC_VECTOR(SCIT_V,6);
SCIT<=TO_STDULOGICVECTOR(SCIT_S);
END PROCESS;

PROCESS(SH_T)
BEGIN
	CASE SH_T IS
		WHEN"0111"=>TXD<='0';
		WHEN"1000"=>TXD<=DIN_LATCH(0);
		WHEN"1001"=>TXD<=DIN_LATCH(1);
		WHEN"1010"=>TXD<=DIN_LATCH(2);
		WHEN"1011"=>TXD<=DIN_LATCH(3);
		WHEN"1100"=>TXD<=DIN_LATCH(4);
		WHEN"1101"=>TXD<=DIN_LATCH(5);
		WHEN"1110"=>TXD<=DIN_LATCH(6);
		WHEN"1111"=>TXD<=DIN_LATCH(7);
		WHEN OTHERS=>TXD<='1';
	END CASE;
END PROCESS;

END RTL;