produce.tan.rpt

vhdl的一个串行序列信号发生器的设计与实现

; Slack ; Required tco ; Actual tco ; From        ; To   ; From Clock ;
+-------+--------------+------------+-------------+------+------------+
; N/A   ; None         ; 8.000 ns   ; pro:u1|sout ; fout ; clk        ;
+-------+--------------+------------+-------------+------+------------+


+-------------------------------------------------------------+
; tpd                                                         ;
+-------+-------------------+-----------------+------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To     ;
+-------+-------------------+-----------------+------+--------+
; N/A   ; None              ; 15.000 ns       ; clk  ; clkout ;
+-------+-------------------+-----------------+------+--------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+------------+---------+-------------+----------+
; Minimum Slack ; Required th ; Actual th  ; From    ; To          ; To Clock ;
+---------------+-------------+------------+---------+-------------+----------+
; N/A           ; None        ; -3.000 ns  ; set     ; pro:u1|sout ; clk      ;
; N/A           ; None        ; -3.000 ns  ; reset   ; pro:u1|sout ; clk      ;
; N/A           ; None        ; -12.000 ns ; data[4] ; pro:u1|sout ; clk      ;
; N/A           ; None        ; -12.000 ns ; data[5] ; pro:u1|sout ; clk      ;
; N/A           ; None        ; -12.000 ns ; data[0] ; pro:u1|sout ; clk      ;
; N/A           ; None        ; -12.000 ns ; data[1] ; pro:u1|sout ; clk      ;
; N/A           ; None        ; -13.000 ns ; data[6] ; pro:u1|sout ; clk      ;
; N/A           ; None        ; -13.000 ns ; data[7] ; pro:u1|sout ; clk      ;
; N/A           ; None        ; -13.000 ns ; data[3] ; pro:u1|sout ; clk      ;
; N/A           ; None        ; -13.000 ns ; data[2] ; pro:u1|sout ; clk      ;
+---------------+-------------+------------+---------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sat Jul 15 21:10:36 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off produce -c produce
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Info: Found combinational loop of 1 nodes
    Info: Node "pro:u1|check~37"
Info: Found combinational loop of 1 nodes
    Info: Node "pro:u1|da[4]~98"
Info: Found combinational loop of 1 nodes
    Info: Node "pro:u1|da[5]~94"
Info: Found combinational loop of 1 nodes
    Info: Node "pro:u1|da[0]~90"
Info: Found combinational loop of 1 nodes
    Info: Node "pro:u1|da[1]~86"
Info: Found combinational loop of 1 nodes
    Info: Node "pro:u1|da[6]~82"
Info: Found combinational loop of 1 nodes
    Info: Node "pro:u1|da[7]~78"
Info: Found combinational loop of 1 nodes
    Info: Node "pro:u1|da[3]~74"
Info: Found combinational loop of 1 nodes
    Info: Node "pro:u1|da[2]~70"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 71.43 MHz between source register "pro:u1|sign[0]" and destination register "pro:u1|sout" (period= 14.0 ns)
    Info: + Longest register to register delay is 9.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC33; Fanout = 14; REG Node = 'pro:u1|sign[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC36; Fanout = 1; COMB Node = 'pro:u1|sout~765'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1|sout'
        Info: Total cell delay = 7.000 ns ( 77.78 % )
        Info: Total interconnect delay = 2.000 ns ( 22.22 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1|sout'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC33; Fanout = 14; REG Node = 'pro:u1|sign[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "pro:u1|sout" (data pin = "data[4]", clock pin = "clk") is 48.000 ns
    Info: + Longest pin to register delay is 47.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_57; Fanout = 3; PIN Node = 'data[4]'
        Info: 2: + IC(0.000 ns) + CELL(9.000 ns) = 11.000 ns; Loc. = LC47; Fanout = 7; COMB LOOP Node = 'pro:u1|da[4]~98'
            Info: Loc. = LC47; Node "pro:u1|da[4]~98"
        Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC45; Fanout = 2; COMB Node = 'pro:u1|check~28'
        Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 29.000 ns; Loc. = LC3; Fanout = 3; COMB Node = 'pro:u1|process0~11'
        Info: 5: + IC(0.000 ns) + CELL(9.000 ns) = 38.000 ns; Loc. = LC43; Fanout = 3; COMB LOOP Node = 'pro:u1|check~37'
            Info: Loc. = LC43; Node "pro:u1|check~37"
        Info: 6: + IC(2.000 ns) + CELL(6.000 ns) = 46.000 ns; Loc. = LC36; Fanout = 1; COMB Node = 'pro:u1|sout~765'
        Info: 7: + IC(0.000 ns) + CELL(1.000 ns) = 47.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1|sout'
        Info: Total cell delay = 41.000 ns ( 87.23 % )
        Info: Total interconnect delay = 6.000 ns ( 12.77 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1|sout'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "fout" through register "pro:u1|sout" is 8.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1|sout'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1|sout'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'fout'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Longest tpd from source pin "clk" to destination pin "clkout" is 15.000 ns
    Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
    Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC61; Fanout = 1; COMB Node = 'clk~6'
    Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'clkout'
    Info: Total cell delay = 14.000 ns ( 93.33 % )
    Info: Total interconnect delay = 1.000 ns ( 6.67 % )
Info: th for register "pro:u1|sout" (data pin = "set", clock pin = "clk") is -3.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1|sout'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 31; PIN Node = 'set'
        Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1|sout'
        Info: Total cell delay = 9.000 ns ( 90.00 % )
        Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Jul 15 21:10:37 2006
    Info: Elapsed time: 00:00:02