produce.tan.qmsg

vhdl的一个串行序列信号发生器的设计与实现

{ "Info" "ITDB_FULL_TCO_RESULT" "clk fout pro:u1\|sout 8.000 ns register " "Info: tco from clock \"clk\" to destination pin \"fout\" through register \"pro:u1\|sout\" is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { clk } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns pro:u1\|sout 2 REG LC37 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1\|sout'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "0.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pro:u1\|sout 1 REG LC37 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1\|sout'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { pro:u1|sout } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns fout 2 PIN PIN_30 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'fout'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "4.000 ns" { pro:u1|sout fout } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 100.00 % ) " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "4.000 ns" { pro:u1|sout fout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { pro:u1|sout fout } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "4.000 ns" { pro:u1|sout fout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { pro:u1|sout fout } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk clkout 15.000 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"clkout\" is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { clk } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns clk~6 2 COMB LC61 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC61; Fanout = 1; COMB Node = 'clk~6'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "8.000 ns" { clk clk~6 } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns clkout 3 PIN PIN_34 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'clkout'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "4.000 ns" { clk~6 clkout } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns ( 93.33 % ) " "Info: Total cell delay = 14.000 ns ( 93.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 6.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "15.000 ns" { clk clk~6 clkout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "15.000 ns" { clk clk~out clk~6 clkout } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 3.000ns 7.000ns 4.000ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "pro:u1\|sout set clk -3.000 ns register " "Info: th for register \"pro:u1\|sout\" (data pin = \"set\", clock pin = \"clk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { clk } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns pro:u1\|sout 2 REG LC37 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1\|sout'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "0.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns set 1 PIN PIN_84 31 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 31; PIN Node = 'set'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { set } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns pro:u1\|sout 2 REG LC37 1 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1\|sout'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "7.000 ns" { set pro:u1|sout } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 90.00 % ) " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.00 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "10.000 ns" { set pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { set set~out pro:u1|sout } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "10.000 ns" { set pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { set set~out pro:u1|sout } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 21:10:37 2006 " "Info: Processing ended: Sat Jul 15 21:10:37 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}