📄 produce.tan.qmsg
字号:
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pro:u1\|da\[7\]~78 " "Info: Node \"pro:u1\|da\[7\]~78\"" { } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0} } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pro:u1\|da\[3\]~74 " "Info: Node \"pro:u1\|da\[3\]~74\"" { } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0} } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pro:u1\|da\[2\]~70 " "Info: Node \"pro:u1\|da\[2\]~70\"" { } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0} } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 6 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register pro:u1\|sign\[0\] register pro:u1\|sout 71.43 MHz 14.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 71.43 MHz between source register \"pro:u1\|sign\[0\]\" and destination register \"pro:u1\|sout\" (period= 14.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pro:u1\|sign\[0\] 1 REG LC33 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC33; Fanout = 14; REG Node = 'pro:u1\|sign\[0\]'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { pro:u1|sign[0] } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns pro:u1\|sout~765 2 COMB LC36 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC36; Fanout = 1; COMB Node = 'pro:u1\|sout~765'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "8.000 ns" { pro:u1|sign[0] pro:u1|sout~765 } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns pro:u1\|sout 3 REG LC37 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1\|sout'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "1.000 ns" { pro:u1|sout~765 pro:u1|sout } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns ( 77.78 % ) " "Info: Total cell delay = 7.000 ns ( 77.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 22.22 % ) " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "9.000 ns" { pro:u1|sign[0] pro:u1|sout~765 pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "9.000 ns" { pro:u1|sign[0] pro:u1|sout~765 pro:u1|sout } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { clk } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns pro:u1\|sout 2 REG LC37 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1\|sout'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "0.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { clk } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns pro:u1\|sign\[0\] 2 REG LC33 14 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC33; Fanout = 14; REG Node = 'pro:u1\|sign\[0\]'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "0.000 ns" { clk pro:u1|sign[0] } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sign[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sign[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sign[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sign[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "9.000 ns" { pro:u1|sign[0] pro:u1|sout~765 pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "9.000 ns" { pro:u1|sign[0] pro:u1|sout~765 pro:u1|sout } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sign[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sign[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "pro:u1\|sout data\[4\] clk 48.000 ns register " "Info: tsu for register \"pro:u1\|sout\" (data pin = \"data\[4\]\", clock pin = \"clk\") is 48.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "47.000 ns + Longest pin register " "Info: + Longest pin to register delay is 47.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns data\[4\] 1 PIN PIN_57 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_57; Fanout = 3; PIN Node = 'data\[4\]'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { data[4] } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 11.000 ns pro:u1\|da\[4\]~98 2 COMB LOOP LC47 7 " "Info: 2: + IC(0.000 ns) + CELL(9.000 ns) = 11.000 ns; Loc. = LC47; Fanout = 7; COMB LOOP Node = 'pro:u1\|da\[4\]~98'" { { "Info" "ITDB_PART_OF_SCC" "pro:u1\|da\[4\]~98 LC47 " "Info: Loc. = LC47; Node \"pro:u1\|da\[4\]~98\"" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { pro:u1|da[4]~98 } "NODE_NAME" } "" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { pro:u1|da[4]~98 } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 -1 0 } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "9.000 ns" { data[4] pro:u1|da[4]~98 } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns pro:u1\|check~28 3 COMB LC45 2 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC45; Fanout = 2; COMB Node = 'pro:u1\|check~28'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "9.000 ns" { pro:u1|da[4]~98 pro:u1|check~28 } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 29.000 ns pro:u1\|process0~11 4 COMB LC3 3 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 29.000 ns; Loc. = LC3; Fanout = 3; COMB Node = 'pro:u1\|process0~11'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "9.000 ns" { pro:u1|check~28 pro:u1|process0~11 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 38.000 ns pro:u1\|check~37 5 COMB LOOP LC43 3 " "Info: 5: + IC(0.000 ns) + CELL(9.000 ns) = 38.000 ns; Loc. = LC43; Fanout = 3; COMB LOOP Node = 'pro:u1\|check~37'" { { "Info" "ITDB_PART_OF_SCC" "pro:u1\|check~37 LC43 " "Info: Loc. = LC43; Node \"pro:u1\|check~37\"" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { pro:u1|check~37 } "NODE_NAME" } "" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { pro:u1|check~37 } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 14 -1 0 } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "9.000 ns" { pro:u1|process0~11 pro:u1|check~37 } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 46.000 ns pro:u1\|sout~765 6 COMB LC36 1 " "Info: 6: + IC(2.000 ns) + CELL(6.000 ns) = 46.000 ns; Loc. = LC36; Fanout = 1; COMB Node = 'pro:u1\|sout~765'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "8.000 ns" { pro:u1|check~37 pro:u1|sout~765 } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 47.000 ns pro:u1\|sout 7 REG LC37 1 " "Info: 7: + IC(0.000 ns) + CELL(1.000 ns) = 47.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1\|sout'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "1.000 ns" { pro:u1|sout~765 pro:u1|sout } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "41.000 ns ( 87.23 % ) " "Info: Total cell delay = 41.000 ns ( 87.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns ( 12.77 % ) " "Info: Total interconnect delay = 6.000 ns ( 12.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "47.000 ns" { data[4] pro:u1|da[4]~98 pro:u1|check~28 pro:u1|process0~11 pro:u1|check~37 pro:u1|sout~765 pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "47.000 ns" { data[4] data[4]~out pro:u1|da[4]~98 pro:u1|check~28 pro:u1|process0~11 pro:u1|check~37 pro:u1|sout~765 pro:u1|sout } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 9.000ns 7.000ns 7.000ns 9.000ns 6.000ns 1.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "" { clk } "NODE_NAME" } "" } } { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns pro:u1\|sout 2 REG LC37 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 1; REG Node = 'pro:u1\|sout'" { } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "0.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "47.000 ns" { data[4] pro:u1|da[4]~98 pro:u1|check~28 pro:u1|process0~11 pro:u1|check~37 pro:u1|sout~765 pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "47.000 ns" { data[4] data[4]~out pro:u1|da[4]~98 pro:u1|check~28 pro:u1|process0~11 pro:u1|check~37 pro:u1|sout~765 pro:u1|sout } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 9.000ns 7.000ns 7.000ns 9.000ns 6.000ns 1.000ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "produce" "UNKNOWN" "V1" "E:/STUDY/数字电路实验/OVER/实验五/db/produce.quartus_db" { Floorplan "E:/STUDY/数字电路实验/OVER/实验五/" "" "3.000 ns" { clk pro:u1|sout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out pro:u1|sout } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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