produce.hier_info

vhdl的一个串行序列信号发生器的设计与实现

|produce
clk => pro:u1.clk
clk => clkout.DATAIN
set => pro:u1.set
reset => pro:u1.reset
data[0] => pro:u1.data[0]
data[1] => pro:u1.data[1]
data[2] => pro:u1.data[2]
data[3] => pro:u1.data[3]
data[4] => pro:u1.data[4]
data[5] => pro:u1.data[5]
data[6] => pro:u1.data[6]
data[7] => pro:u1.data[7]
fout <= pro:u1.sout
clkout <= clk.DB_MAX_OUTPUT_PORT_TYPE


|produce|pro:u1
clk => sign[2].CLK
clk => sign[1].CLK
clk => sign[0].CLK
clk => sout~reg0.CLK
clk => sign[3].CLK
set => comb~0.IN0
set => comb~2.IN1
set => sign~4.IN0
set => sout~2.OUTPUTSELECT
set => da[6].LATCH_ENABLE
set => da[5].LATCH_ENABLE
set => da[4].LATCH_ENABLE
set => da[3].LATCH_ENABLE
set => da[2].LATCH_ENABLE
set => da[1].LATCH_ENABLE
set => da[0].LATCH_ENABLE
set => process0~0.OUTPUTSELECT
set => da[7].LATCH_ENABLE
reset => sign~4.IN1
reset => sout~1.OUTPUTSELECT
data[0] => da[0].DATAIN
data[1] => da[1].DATAIN
data[2] => da[2].DATAIN
data[3] => da[3].DATAIN
data[4] => da[4].DATAIN
data[5] => da[5].DATAIN
data[6] => da[6].DATAIN
data[7] => da[7].DATAIN
sout <= sout~reg0.DB_MAX_OUTPUT_PORT_TYPE