produce.map.qmsg

vhdl的一个串行序列信号发生器的设计与实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 21:10:24 2006 " "Info: Processing started: Sat Jul 15 21:10:24 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off produce -c produce " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off produce -c produce" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pro.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pro.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pro-pro_arth " "Info: Found design unit 1: pro-pro_arth" {  } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pro " "Info: Found entity 1: pro" {  } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "produce.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file produce.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 produce-produce_arth " "Info: Found design unit 1: produce-produce_arth" {  } { { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 produce " "Info: Found entity 1: produce" {  } { { "produce.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "produce " "Info: Elaborating entity \"produce\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pro pro:u1 " "Info: Elaborating entity \"pro\" for hierarchy \"pro:u1\"" {  } { { "produce.vhd" "u1" { Text "E:/STUDY/数字电路实验/OVER/实验五/produce.vhd" 26 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data pro.vhd(21) " "Warning (10492): VHDL Process Statement warning at pro.vhd(21): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "da pro.vhd(22) " "Warning (10492): VHDL Process Statement warning at pro.vhd(22): signal \"da\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "da pro.vhd(23) " "Warning (10492): VHDL Process Statement warning at pro.vhd(23): signal \"da\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "da pro.vhd(18) " "Warning (10631): VHDL Process Statement warning at pro.vhd(18): signal or variable \"da\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"da\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "check pro.vhd(18) " "Warning (10631): VHDL Process Statement warning at pro.vhd(18): signal or variable \"check\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"check\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "pro.vhd" "" { Text "E:/STUDY/数字电路实验/OVER/实验五/pro.vhd" 18 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "3 " "Info: Ignored 3 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "3 " "Info: Ignored 3 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "19 " "Info: Implemented 19 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 21:10:27 2006 " "Info: Processing ended: Sat Jul 15 21:10:27 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}