produce.map.rpt

vhdl的一个串行序列信号发生器的设计与实现

; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 19                   ;
; Total registers      ; 5                    ;
; I/O pins             ; 13                   ;
; Shareable expanders  ; 1                    ;
; Parallel expanders   ; 1                    ;
; Maximum fan-out node ; set                  ;
; Maximum fan-out      ; 13                   ;
; Total fan-out        ; 88                   ;
; Average fan-out      ; 2.67                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |produce                   ; 19         ; 13   ; |produce            ;
;    |pro:u1|                ; 18         ; 0    ; |produce|pro:u1     ;
+----------------------------+------------+------+---------------------+


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; pro:u1|da[7]                                  ;   ;
; pro:u1|da[6]                                  ;   ;
; pro:u1|da[5]                                  ;   ;
; pro:u1|da[4]                                  ;   ;
; pro:u1|da[3]                                  ;   ;
; pro:u1|da[2]                                  ;   ;
; pro:u1|da[1]                                  ;   ;
; pro:u1|da[0]                                  ;   ;
; pro:u1|check                                  ;   ;
; Number of user-specified and inferred latches ; 9 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+-------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: pro:u1|lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+----------------------------------------+
; Parameter Name         ; Value       ; Type                                   ;
+------------------------+-------------+----------------------------------------+
; LPM_WIDTH              ; 4           ; Untyped                                ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                ;
; LPM_DIRECTION          ; ADD         ; Untyped                                ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                ;
; LPM_PIPELINE           ; 0           ; Untyped                                ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                ;
; REGISTERED_AT_END      ; 0           ; Untyped                                ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                     ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                                ;
; USE_WYS                ; OFF         ; Untyped                                ;
; STYLE                  ; FAST        ; Untyped                                ;
; CBXI_PARAMETER         ; add_sub_3kh ; Untyped                                ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                         ;
+------------------------+-------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/STUDY/数字电路实验/OVER/实验五/produce.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sat Jul 15 21:10:24 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off produce -c produce
Info: Found 2 design units, including 1 entities, in source file pro.vhd
    Info: Found design unit 1: pro-pro_arth
    Info: Found entity 1: pro
Info: Found 2 design units, including 1 entities, in source file produce.vhd
    Info: Found design unit 1: produce-produce_arth
    Info: Found entity 1: produce
Info: Elaborating entity "produce" for the top level hierarchy
Info: Elaborating entity "pro" for hierarchy "pro:u1"
Warning (10492): VHDL Process Statement warning at pro.vhd(21): signal "data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at pro.vhd(22): signal "da" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at pro.vhd(23): signal "da" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at pro.vhd(18): signal or variable "da" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "da" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at pro.vhd(18): signal or variable "check" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "check" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 3 buffer(s)
    Info: Ignored 3 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 33 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 2 output pins
    Info: Implemented 19 macrocells
    Info: Implemented 1 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Sat Jul 15 21:10:27 2006
    Info: Elapsed time: 00:00:05