produce.fit.eqn

vhdl的一个串行序列信号发生器的设计与实现

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--A1L3 is clk~6 at LC61
A1L3_or_out = clk;
A1L3 = A1L3_or_out;


--B1_sign[0] is pro:u1|sign[0] at LC33
B1_sign[0]_p1_out = !B1_sign[1] & !B1_sign[2] & B1_sign[3] & !B1_sign[0];
B1_sign[0]_or_out = B1_sign[0]_p1_out;
B1_sign[0]_reg_input = !B1_sign[0]_or_out;
B1_sign[0] = TFFE(B1_sign[0]_reg_input, GLOBAL(clk), !B1L19, , );


--B1L6 is pro:u1|da[2]~70 at LC1
B1L6_p1_out = data[2] & set;
B1L6_p2_out = !set & B1L6;
B1L6_p3_out = data[2] & B1L6;
B1L6_or_out = B1L6_p1_out # B1L6_p2_out # B1L6_p3_out;
B1L6 = B1L6_or_out;


--B1L7 is pro:u1|da[3]~74 at LC34
B1L7_p1_out = data[3] & set;
B1L7_p2_out = !set & B1L7;
B1L7_p3_out = data[3] & B1L7;
B1L7_or_out = B1L7_p1_out # B1L7_p2_out # B1L7_p3_out;
B1L7 = B1L7_or_out;


--B1L11 is pro:u1|da[7]~78 at LC35
B1L11_p1_out = data[7] & set;
B1L11_p2_out = !set & B1L11;
B1L11_p3_out = data[7] & B1L11;
B1L11_or_out = B1L11_p1_out # B1L11_p2_out # B1L11_p3_out;
B1L11 = B1L11_or_out;


--B1L10 is pro:u1|da[6]~82 at LC38
B1L10_p1_out = data[6] & set;
B1L10_p2_out = !set & B1L10;
B1L10_p3_out = data[6] & B1L10;
B1L10_or_out = B1L10_p1_out # B1L10_p2_out # B1L10_p3_out;
B1L10 = B1L10_or_out;


--B1L5 is pro:u1|da[1]~86 at LC39
B1L5_p1_out = data[1] & set;
B1L5_p2_out = !set & B1L5;
B1L5_p3_out = data[1] & B1L5;
B1L5_or_out = B1L5_p1_out # B1L5_p2_out # B1L5_p3_out;
B1L5 = B1L5_or_out;


--B1L4 is pro:u1|da[0]~90 at LC40
B1L4_p1_out = data[0] & set;
B1L4_p2_out = !set & B1L4;
B1L4_p3_out = data[0] & B1L4;
B1L4_or_out = B1L4_p1_out # B1L4_p2_out # B1L4_p3_out;
B1L4 = B1L4_or_out;


--B1L9 is pro:u1|da[5]~94 at LC48
B1L9_p1_out = data[5] & set;
B1L9_p2_out = !set & B1L9;
B1L9_p3_out = data[5] & B1L9;
B1L9_or_out = B1L9_p1_out # B1L9_p2_out # B1L9_p3_out;
B1L9 = B1L9_or_out;


--B1L8 is pro:u1|da[4]~98 at LC47
B1L8_p1_out = data[4] & set;
B1L8_p2_out = !set & B1L8;
B1L8_p3_out = data[4] & B1L8;
B1L8_or_out = B1L8_p1_out # B1L8_p2_out # B1L8_p3_out;
B1L8 = B1L8_or_out;


--B1L1 is pro:u1|check~21 at LC46
B1L1_p0_out = B1L11 & B1L7 & B1L10;
B1L1_p2_out = !B1L11 & B1L7 & !B1L10;
B1L1_p3_out = B1L11 & !B1L7 & !B1L10;
B1L1_p4_out = !B1L11 & !B1L7 & B1L10;
B1L1_or_out = B1L1_p0_out # B1L1_p2_out # B1L1_p3_out # B1L1_p4_out;
B1L1 = B1L6 $ B1L1_or_out;


--B1L2 is pro:u1|check~28 at LC45
B1L2_p0_out = B1L9 & B1L4 & B1L8;
B1L2_p2_out = !B1L9 & B1L4 & !B1L8;
B1L2_p3_out = B1L9 & !B1L4 & !B1L8;
B1L2_p4_out = !B1L9 & !B1L4 & B1L8;
B1L2_or_out = B1L2_p0_out # B1L2_p2_out # B1L2_p3_out # B1L2_p4_out;
B1L2 = B1L5 $ B1L2_or_out;


--B1L12 is pro:u1|process0~11 at LC3
B1L12_p1_out = set & B1L1 & !B1L2;
B1L12_p2_out = set & !B1L1 & B1L2;
B1L12_or_out = B1L12_p1_out # B1L12_p2_out;
B1L12 = B1L12_or_out;


--B1_sign[1] is pro:u1|sign[1] at LC44
B1_sign[1]_or_out = B1_sign[0];
B1_sign[1]_reg_input = B1_sign[1] $ B1_sign[1]_or_out;
B1_sign[1] = DFFE(B1_sign[1]_reg_input, GLOBAL(clk), !B1L19, , );


--B1L3 is pro:u1|check~37 at LC43
B1L3_p1_out = B1L12 & B1L19;
B1L3_p2_out = B1L3 & !reset & !set;
B1L3_p3_out = B1L12 & B1L3;
B1L3_or_out = B1L3_p1_out # B1L3_p2_out # B1L3_p3_out;
B1L3 = B1L3_or_out;


--B1_sign[2] is pro:u1|sign[2] at LC42
B1_sign[2]_p1_out = B1_sign[1] & B1_sign[0];
B1_sign[2]_or_out = B1_sign[2];
B1_sign[2]_reg_input = B1_sign[2]_p1_out $ B1_sign[2]_or_out;
B1_sign[2] = DFFE(B1_sign[2]_reg_input, GLOBAL(clk), !B1L19, , );


--B1_sign[3] is pro:u1|sign[3] at LC41
B1_sign[3]_p1_out = B1_sign[2] & B1_sign[1] & B1_sign[0];
B1_sign[3]_or_out = B1_sign[3];
B1_sign[3]_reg_input = B1_sign[3]_p1_out $ B1_sign[3]_or_out;
B1_sign[3] = DFFE(B1_sign[3]_reg_input, GLOBAL(clk), !set, !reset, );


--B1_sout is pro:u1|sout at LC37
B1_sout_p0_out = !B1_sign[1] & B1_sign[2] & !B1_sign[0] & B1L8;
B1_sout_p1_out = B1L5 & !B1_sign[1] & !B1_sign[2] & B1_sign[0];
B1_sout_p2_out = !B1_sign[1] & !B1_sign[2] & !B1_sign[0] & !B1_sign[3] & B1L4;
B1_sout_p4_out = !B1_sign[1] & B1_sign[2] & B1_sign[0] & B1L9;
B1_sout_or_out = B1L20 # B1_sout_p0_out # B1_sout_p1_out # B1_sout_p2_out # B1_sout_p4_out;
B1_sout_reg_input = B1_sout_or_out;
B1_sout_p3_out = !reset & !set;
B1_sout = DFFE(B1_sout_reg_input, GLOBAL(clk), , , B1_sout_p3_out);


--B1L20 is pro:u1|sout~765 at LC36
B1L20_p0_out = B1_sign[1] & B1_sign[2] & !B1_sign[0] & B1L10;
B1L20_p1_out = B1L3 & B1_sign[3] & !B1_sign[1] & !B1_sign[2] & !B1_sign[0];
B1L20_p2_out = B1_sign[1] & !B1_sign[2] & !B1_sign[0] & B1L6;
B1L20_p3_out = B1_sign[1] & !B1_sign[2] & B1_sign[0] & B1L7;
B1L20_p4_out = B1_sign[1] & B1_sign[2] & B1_sign[0] & B1L11;
B1L20 = B1L20_p0_out # B1L20_p1_out # B1L20_p2_out # B1L20_p3_out # B1L20_p4_out;


--B1L19 is pro:u1|sout~756sexp at SEXP33
B1L19 = EXP(!reset & !set);


--clk is clk at PIN_83
--operation mode is input

clk = INPUT();


--set is set at PIN_84
--operation mode is input

set = INPUT();


--reset is reset at PIN_1
--operation mode is input

reset = INPUT();


--data[0] is data[0] at PIN_63
--operation mode is input

data[0] = INPUT();


--data[1] is data[1] at PIN_61
--operation mode is input

data[1] = INPUT();


--data[2] is data[2] at PIN_60
--operation mode is input

data[2] = INPUT();


--data[3] is data[3] at PIN_58
--operation mode is input

data[3] = INPUT();


--data[4] is data[4] at PIN_57
--operation mode is input

data[4] = INPUT();


--data[5] is data[5] at PIN_56
--operation mode is input

data[5] = INPUT();


--data[6] is data[6] at PIN_55
--operation mode is input

data[6] = INPUT();


--data[7] is data[7] at PIN_54
--operation mode is input

data[7] = INPUT();


--clkout is clkout at PIN_34
--operation mode is output

clkout = OUTPUT(A1L3);


--fout is fout at PIN_30
--operation mode is output

fout = OUTPUT(B1_sout);