top.v

DE1-FPGA-Board

/////////////////////////////////////////////////////////////////////////////
// FPGA PACMAN TOP
//
// Version : beta2
//
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use. 
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2003. 5. 8 Altera FPGA modification by Katsumi Degawa
// 2003. 9.26 The problem which became a red screen with 
//            Quartus2v3.0 was modified.  T.satou
// 2004. 5.25 psPAD_top(V.2.00) was included K. Degawa
//
/////////////////////////////////////////////////////////////////////////////

module top(
// Universal Video I/F
VGA_R,
VGA_G,
VGA_B,
n_HSYNC,
n_VSYNC,
//ROM interface
O_ROM_AB,
I_ROM_DB,
O_ROM_OEn,
O_ROM_CSn,
O_ROM_WEn,
O_ROM_Reset_n,
//Sound
DAC_L,
DAC_R,
//Controll switches
PSW,
PS2_DAT,
PS2_CLK,
//50MHz CLOCK input to generate 18.432MHz Clock
I_CLK_50M,
// SOUND DE1-Terasic WM8731
I2C_SDAT,						//	I2C Data
I2C_SCLK,						//	I2C Clock
AUD_ADCLRCK,					//	Audio CODEC ADC LR Clock
AUD_XCK,						//	Audio CODEC Chip Clock
AUD_DACLRCK,					//	Audio CODEC DAC LR Clock
AUD_DACDAT,						//	Audio CODEC DAC Data
AUD_BCLK						//	Audio CODEC Bit-Stream Clock
);

/////////////////////////////////////////////////////////////////////////////
// module I/O assign
/////////////////////////////////////////////////////////////////////////////

//Sound
output DAC_L,DAC_R;

//Controll switches
input  [0:0] PSW;
inout  PS2_DAT;
inout  PS2_CLK;
//50MHz CLOCK input to generate 18.432MHz Clock
input  I_CLK_50M;
// SOUND DE1-Terasic WM8731
inout  I2C_SDAT;				//	I2C Data
output I2C_SCLK;				//	I2C Clock
output AUD_ADCLRCK;				//	Audio CODEC ADC LR Clock
output AUD_XCK;					//	Audio CODEC Chip Clock
output AUD_DACLRCK;				//	Audio CODEC DAC LR Clock
output AUD_DACDAT;				//	Audio CODEC DAC Data
inout  AUD_BCLK;				//	Audio CODEC Bit-Stream Clock

// Universal Video I/F
output [2:0]VGA_R; 
output [2:0]VGA_G; 
output [2:1]VGA_B;
output n_HSYNC,n_VSYNC;

// code / pattern ROM interface
output [21:0]O_ROM_AB;
input  [7:0]I_ROM_DB;
output O_ROM_OEn;
output O_ROM_CSn;
output O_ROM_WEn;
output O_ROM_Reset_n;

/////////////////////////////////////////////////////////////////////////////
// clock generator
/////////////////////////////////////////////////////////////////////////////
wire CLK18_432M;
wire ZRESET;
Clock_Pll C_PLL(
	.areset(~PSW[0]),
	.inclk0(I_CLK_50M),
	.c0(CLK18_432M),
	.locked(ZRESET)
);
wire CLK12_288M;
wire CLK6_144M;
clock BASE_CLOCK(
	.I_CLK_18M(CLK18_432M),
	.O_CLK_12M(CLK12_288M),
	.O_CLK_06M(CLK6_144M),
	.O_CLK_06Mn()
);

// base & video pixel clock
wire pixel_clk = CLK6_144M;

/////////////////////////////////////////////////////////////////////////////
// Z80 core
/////////////////////////////////////////////////////////////////////////////

wire [7:0] ZDO,ZDI;
//output
wire [15:0] ZA;
wire ZMREQ,ZIORQ,ZM1,ZRD,ZWR,ZRFSH;
wire ZWO;
//input
wire ZINT;
wire ZNMI = 1'b1;

wire ZWAIT = ~(csvram & hcnt[1] & ~ZRD); // wait controll
wire Z80CLK2 = pixel_clk;         		 // 6MHz
wire Z80CLK = ~hcnt[0];

Z80IP CPU(
	.CLK2X(Z80CLK2),
	.CLK(Z80CLK),
	.RESET_N(ZRESET),
	.INT_N(ZINT),
	.NMI_N(ZNMI),
	.A(ZA),
	.DOUT(ZDO),
	.DIN(ZDI),
	.M1_N(ZM1),
	.MREQ_N(ZMREQ),
	.IORQ_N(ZIORQ),
	.RD_N(ZRD),
	.WR_N(ZWR),
	.WAIT_N(ZWAIT),
	.BUSWO(ZWO),
	.RFSH_N(ZRFSH),
	.HALT_N()
);

/////////////////////////////////////////////////////////////////////////////
// address decoder
/////////////////////////////////////////////////////////////////////////////

wire flip;
wire in0,in1,dsw1,dsw2;
wire wr0,wr1;
wire snd_on;
wire csxyram , csvram;
wire csrom;
adec pacman_adec(
// inputs
	.PCLK(pixel_clk),
	.A(ZA),
	.n_MREQ(ZMREQ),
	.D0I(ZDO[0]),
	.n_RD(ZRD),
	.n_RFSH(ZRFSH),
	.RST(1'b0),
// decode output
	.ROM(csrom),
	.RAM(csvram),
	.IN0(in0),
	.IN1(in1),
	.DSW1(dsw1),
	.DSW2(dsw2),
	.WR0(wr0),
	.WR1(wr1),	// 5050-505f.W sound frequency   / volume
	.WR2(csxyram),	// 5060-506f.W object X,Y RAM
	.WDT(),	// 50c0-50ff.W Watchdog timer reset
// latched register
	.IRQ(irqen),	// 5000.W      IRQ enable (clear)
	.SOUND_ON(snd_on),// 5001.W      sound enable
	.FLIP(flip),	// 5003.W      flip
	.LAMP1P(),	// 5004.W      1P start lamp
	.LAMP2P(),	// 5005.W      2P start lamp
	.COINLK(),	// 5006.W      coin lockout
	.COINUP()	// 5007.W      coin countup
);

/////////////////////////////////////////////////////////////////////////////
// CPU PROM to shared ROM interface
/////////////////////////////////////////////////////////////////////////////
wire [18:0] cpu_a;
reg [7:0] cpu_rd;
wire [7:0] rom_do = csrom ? cpu_rd : 8'h00;
assign cpu_a[15:0]  = ZA;
assign cpu_a[18:16] = 0;

/////////////////////////////////////////////////////////////////////////////
// controller IN / DIP switch I/F
/////////////////////////////////////////////////////////////////////////////
wire C1, S1, L1, R1, U1, D1;
wire C2, S2, L2, R2, U2, D2;

KeybControl KCont(
.CLOCK18(CLK18_432M),
.PS2_DAT(PS2_DAT),
.PS2_CLK(PS2_CLK),
.iRST_N(ZRESET),
.O_COIN1(C1),
.O_1P_START(S1),
.O_1P_LE(L1),
.O_1P_RI(R1),
.O_1P_UP(U1),
.O_1P_DN(D1),
.O_COIN2(C2),
.O_2P_START(S2),
.O_2P_LE(L2),
.O_2P_RI(R2),
.O_2P_UP(U2),
.O_2P_DN(D2)
);
wire [7:0] inp_do;
inport pacman_inport(
// inputs
	.LEFT1(~L1),
	.RIGHT1(~R1),
	.UP1(~U1),
	.DOWN1(~D1),
	.LEFT2(~L2),
	.RIGHT2(~R2),
	.UP2(~U2),
	.DOWN2(~D2),
	.START1(~S1),
	.START2(~S2),
	.COIN1(~C1),
	.COIN2(~C2),
	.CREDIT(1'b1),
	.TEST(1'b1),
	.TABLE(1'b1),
//enables
	.IN0(in0),
	.IN1(in1),
	.DSW1(dsw1),
	.DSW2(dsw2),
//output
	.DO(inp_do)	
);

/////////////////////////////////////////////////////////////////////////////
// VIDEO hardware interface
/////////////////////////////////////////////////////////////////////////////
wire [8:0] hcnt;
wire hsync,vsync;
wire [7:0] vdo;
wire vblank;
wire [2:0] red;
wire [2:0] green;
wire [1:0] blue;
reg  [7:0] pd;  //pattern ROM data
wire [12:0] pa; //patterm ROM address

// viode & work RAM I/F
wire [11:0] AB;
wire [7:0] DB_I;
wire tile_we , col_we , wram_we;
wire tile_cs , col_cs , wram_cs;
// line ram
wire [7:0] lram_a;
wire [3:0] lram_di;
wire [3:0] lram_do;
wire kram_cs,lram_we;
// object position ram
wire [7:0] pram_di,pram_do;
wire pram_we;
wire [7:0] clut_a;
wire [3:0] clut_d;
wire [3:0] pal_a;

video vh(
	.A(ZA[11:0]),
	.csvram(csvram),
	.csxyram(csxyram),
	.n_rd(ZRD),
	.di(ZDO),
	.vdo(vdo),
	.WAIT_N(ZWAIT),
	.pclk(pixel_clk),
	.flip(flip),
	.vb(vblank),
	.hc(hcnt),
	.hs(hsync),
	.vs(vsync),
//	.r(red),
//	.g(green),
//	.b(blue),
	.CA(pa),
	.CD(pd),   // Bug Fix  .CD(RD) => .CD(pd)
// CPU & VIDEO memory bus , & sound timming address
	.AB(AB), 
// VIDEO memory bus & controll
	.DB_I(DB_I),
	.TRAM_WE(tile_we),
	.TRAM_CS(tile_cs),
	.CRAM_WE(col_we),
	.CRAM_CS(col_cs),
	.WRAM_WE(wram_we),
	.WRAM_CS(wram_cs),
// line ram
	.LRAM_A(lram_a),
	.LRAM_DI(lram_di),
	.LRAM_DO(lram_do),
	.LRAM_CS(lram_cs),
	.LRAM_WE(lram_we),
// object position ram
	.PRAM_DI(pram_di),
	.PRAM_DO(pram_do),
	.PRAM_WE(pram_we),
// CLUT ROM
	.CLUT_A(clut_a),
	.CLUT_DI(clut_d),
// PaletteROM
	.PAL_A(pal_a)
);

/////////////////////////////////////////////////////////////////////////////
// IRQ & IRQ vector
/////////////////////////////////////////////////////////////////////////////

wire [7:0] irq_do;
wire vector_enable;
irq pacman_irqvector(
//inputs
	.n_M1(ZM1),
	.n_IORQ(ZIORQ),
	.n_WR(ZWR),
	.IRQEN(irqen),
	.IRQTRG(vblank),
	.DI(ZDO),
//outputs
	.n_IRQ(ZINT),
	.DO(irq_do),
	.DE(vector_enable)
);

/////////////////////////////////////////////////////////////////////////////
// sound
/////////////////////////////////////////////////////////////////////////////

wire [9:0] wave_out;
wire [8:0] wave_a;
wire [3:0] wave_d;
sound sound(
	.AB(ZA[3:0]),
//	.AB(AB[3:0]),
	.DI(ZDO[3:0]),
	.WR0(wr0),
	.WR1(wr1),
	.PCLK(pixel_clk),
	.SOUND_ON(snd_on),
	.HC(hcnt[5:0]),
//
	.DAO(wave_out),
	.WA(wave_a),
	.WDI(wave_d)
);

/////////////////////////////////////////////////////////////////////////////
// memory 
/////////////////////////////////////////////////////////////////////////////
wire [7:0] pal_d;

Amemory ALTERAMemory(
  .CLK_12M(CLK12_288M),
  .AB(AB),.DB_I(ZDO),.DB_O(DB_I),
  .TILE_CS(tile_cs),.TILE_WE(tile_we),
  .COL_CS(col_cs),.COL_WE(col_we),
  .WORK_CS(wram_cs),.WORK_WE(wram_we),
  .PWE(pram_we),.PDI(pram_do),.PDO(pram_di),
  .LA(lram_a),.LDO(lram_di),.LDI(lram_do),.LCS(lram_cs),.LWE(lram_we),
//  SA,S0DI,S0DO,S1DI,S1DO,SWE,
  .WA(wave_a),.WDO(wave_d),
  .CLUTA(clut_a),.CLUT_DO(clut_d),
  .PAL_A(pal_a),.PAL_DO(pal_d)
);
// R,G,B output signal
assign {blue,green,red} = pal_d;

/////////////////////////////////////////////////////////////////////////////
// ROM interface
/////////////////////////////////////////////////////////////////////////////

reg [18:0] rom_a;
always @(posedge pixel_clk)
begin
	if(~hcnt[0])
	begin
		// latch CPU data & switch video address
		cpu_rd <= I_ROM_DB;
		rom_a  <= { 6'b000011 ,  pa}; //06000-07fff
	end else begin
		// latch pixel data & switch cpu address
		pd    <= I_ROM_DB;
		rom_a <= cpu_a;
	end
end

assign O_ROM_AB[18:0]  = rom_a[18:0];
assign O_ROM_AB[21:19] = 3'b000;
assign O_ROM_OEn 	   = 1'b0;//FLASH Output Enable
assign O_ROM_CSn 	   = 1'b0;//FLASH Chip Select
assign O_ROM_WEn 	   = 1'b1;//FLASH Write Enable
assign O_ROM_Reset_n   = 1'b1;//FLASH Reset

/////////////////////////////////////////////////////////////////////////////
// data bus multiplexer
/////////////////////////////////////////////////////////////////////////////

assign ZDI = vdo | rom_do | inp_do | irq_do;

/////////////////////////////////////////////////////////////////////////////
// Video encoder
/////////////////////////////////////////////////////////////////////////////
wire [7:0] rgb_in = { red,green,blue };

venc pacman_video_encoder(
	.pclk(pixel_clk),
	.dclk(CLK12_288M),
	.rgb8_in(rgb_in),
	.hs_in(hsync),
	.vs_in(vsync),
//
	.r_out(VGA_R),
	.g_out(VGA_G),
	.b_out(VGA_B),
	.hs_out(n_HSYNC),
	.vs_out(n_VSYNC)
);

/////////////////////////////////////////////////////////////////////////////
// SOUND DAC interface
/////////////////////////////////////////////////////////////////////////////

// Sigma Delta :  sampling rate = 37.53KHz
wire dac_out;
dac dac(.DACout(dac_out),.DACin(wave_out[9:2]),.Clk(CLK18_432M),.Reset(~ZRESET));

// DAC output PIN assign
assign DAC_L = dac_out;
assign DAC_R = dac_out;

////////////////////////////////////////////////////
// SOUND DE1-Terasic WM8731
////////////////////////////////////////////////////
wire I2C_END;
I2C_AV_Config 		u10	(	//	Host Side
							.o_I2C_END(I2C_END),
							.iCLK(CLK18_432M),
							.iRST_N(ZRESET),
							//	I2C Side
							.I2C_SCLK(I2C_SCLK),
							.I2C_SDAT(I2C_SDAT)	);
//--------------------------------
AUDIO_DAC 			u11	(
//							.Sound_L(16'b0000000000000000),
							.Sound_L({2'b00,wave_out[9:2],6'b000000}),
//-----
//							.Sound_R(16'b0000000000000000),
							.Sound_R({2'b00,wave_out[9:2],6'b000000}),
							//	Audio Side
							.oAUD_XCK(AUD_XCK),
							.ioAUD_BCLK(AUD_BCLK),
							.oAUD_DACDAT(AUD_DACDAT),
							.oAUD_DACLRCK(AUD_DACLRCK),
							.oAUD_ADCLRCK(AUD_ADCLRCK),
							//	Control Signals
				            .iCLK(CLK18_432M),
							.iRST_N(ZRESET & I2C_END));


endmodule