amemory.v

DE1-FPGA-Board

/////////////////////////////////////////////////////////////////////////////
// FPGA PACMAN memory interface for ALTERA CYCLONE
//
// Version :
//
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use. 
// An author does no guarantee about this program.
// You can use this under your own risk. 
//
// 2003. 2. 6 beta2 Created
// 2003. 5. 8 Altera FPGA modification by Katsumi Degawa
// 2003. 9.26 Separate DualPort to SinglePort Memory
//            to escape DPRAM portB probrem by T.Satoh
//
/////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////
// internal memory
/////////////////////////////////////////////////////////////////////////////

//
// Internal RAMs used 'BlockSelectRAM'
//
// 1.tilemap code RAM
// 2.tilemap color RAM
// 3.work & object RAM
// 4.object position RAM
// 5.object line RAM
// 6.sound waveform ROM
// 7.color lockup table ROM
// 8.palette ROM
//
// External ROM
//
// 9.CPU code ROM
// 10.object pattern ROM
//

module Amemory(
//
  CLK_12M,
// Sahred Address & Data(Out) Bus
  AB,DB_I,DB_O,
  TILE_CS,TILE_WE, COL_CS,COL_WE, WORK_CS,WORK_WE,
  PWE,PDI,PDO,
  LA,LDO,LDI,LCS,LWE,
//  SA,S0DI,S0DO,S1DI,S1DO,SWE,
  WA,WDO,
  CLUTA,CLUT_DO,
  PAL_A,PAL_DO
);

/////////////////////////////////////////////////////////////////////////////
// module I/O assign
/////////////////////////////////////////////////////////////////////////////
input CLK_12M;
input [11:0] AB;
input [7:0] DB_I;
output [7:0] DB_O;

// TileCode RAM
input TILE_CS,TILE_WE;
// TileColor RAM
input COL_CS,COL_WE;
// Work/ObjectAttribute RAM
input WORK_CS,WORK_WE;
// Object Position RAM
input PWE;
input [7:0] PDI;
output [7:0] PDO;
// Object Line RAM
input [7:0] LA;
input [3:0] LDI;
output [3:0] LDO;
input LCS,LWE;
// sound Register RAM
// input [3:0] SA;
// output [3:0] S0DO , S1DO;
// input  [3:0] S0DI , S1DI;
// input SWE;
// sound WaveForm ROM
input [8:0] WA;
output [3:0] WDO;
//ColorLookup ROM
input [7:0] CLUTA;
output [3:0] CLUT_DO;
input [3:0] PAL_A;
output [7:0] PAL_DO;

/////////////////////////////////////////////////////////////////////////////
// Video RAM
/////////////////////////////////////////////////////////////////////////////

wire [7:0] tile_do2 , col_do2 , wram_do2;

wire [7:0] tile_do = (TILE_CS)? tile_do2:8'h00;
wire [7:0] col_do  = (COL_CS)?  col_do2 :8'h00;
wire [7:0] wram_do = (WORK_CS)? wram_do2:8'h00;

assign DB_O = tile_do | col_do | wram_do;

//
// 1.tilemap code RAM
//
// Area    : 4000-43ff
// Size    : 8bit x 1024word
// Address : AB[9:0]
// Dout    : DB_O (shared)
// Din     : DB_I
// CS      : TILE_CS
// WE      : TILE_WE
// 
alt_ram_1024_8 RAM_4N_4K(
.clock(CLK_12M),
.address(AB[9:0]),
.q(tile_do2),
.data(DB_I),
.enable(TILE_CS),
.wren(TILE_WE)
);

//
// 2.tilemap color RAM
//
// parts   : 
// Area    : 4400-47ff
// Size    : 8bit x 1024word
// Address : AB[9:0]
// Dout    : DB_O (shared)
// Din     : DB_I
// CS      : COL_CS
// WE      : COL_WE
// 
alt_ram_1024_8 RAM_4P_4L(
.clock(CLK_12M),
.address(AB[9:0]),
.q(col_do2),
.data(DB_I),
.enable(COL_CS),
.wren(COL_WE)
);

//
// 3.work & object RAM
//
// parts   : 4R,4M
// Area    : 4c00-4fff
// Size    : 8bit x 1024word
// Address : AB[9:0]
// Dout    : DB_O (shared)
// Din     : DB_I
// CS      : WORK_CS
// WE      : WORK_WE
// 
alt_ram_1024_8 RAM_4R_4M(
.clock(CLK_12M),
.address(AB[9:0]),
.q(wram_do2),
.data(DB_I),
.enable(WORK_CS),
.wren(WORK_WE)
);

//
// 4.object position RAM
//
// parts   : 3F,3E
// Area    : 5060-506f
// Size    : 8bit x 16word
// Address : AB[3:0]
// Dout    : PDO (separate)
// Din     : PDI (separate)
// CS      : always select
// WE      : PWE
// 
alt_ram_16_8 RAM_3F_3E(
.clock(CLK_12M),
.address(AB[3:0]),
.q(PDO),.data(PDI),
.wren(PWE)
);

//
// 5.object line RAM
//
// parts   : (1A,1B,1C,1D) or (2A,2B,2B,2D)
// Area    : none
// Size    : 4bit x 256word
// Address : LA
// Dout    : LDO (separate)
// Din     : LDI (separate)
// CS      : LCS
// WE      : LWE (6MHz)
//
// note : LDO is latched LWE fall,so read data should be setup before LWE fall.
//
wire [3:0] LDO_2;
assign LDO = (LCS)? LDO_2 :4'b0000;
alt_ram_256_4 RAM_1A_1B_1C_1D(
.clock(~CLK_12M),
.address(LA),
.q(LDO_2),
.data(LDI),
.wren(LWE),
.enable(LCS)
);

//
// 6.sound waveform ROM
//
// parts   : 1M
// Area    : none
// Size    : 4bit x 256word
// Address : WA
// Dout    : WDO
// CS      : always select
//
//wire [9:0] wfa = {1'b0,WA}; // resize to 256x8bit
PAC_WAV_ROM WAVEFORM_ROM00(
.clock(CLK_12M),
//.address(wfa), // B.Mayer
.address(WA),
.q(WDO)
);

//
// 7.color lockup table ROM
//
wire [7:0] clut_do8;
assign CLUT_DO = clut_do8[3:0];
PAC_clut_ROM clut_rom00 ( .clock(~CLK_12M),.address(CLUTA),.q(clut_do8));

//
// 8.palette ROM
//
//PAC_pal_ROM pal_rom00 (.clock(CLK_12M),.address(PAL_A),.q(PAL_DO) );
PAC_pal_ROM pal_rom00 (.clock(CLK_12M),.address({1'b0,PAL_A}),.q(PAL_DO));//B.Mayer

//
// ----- PALETTE RAM async. version -----
//
// BSRAM version make half pixel delay to RGB output.
// fill a ROM code here if you dislike that.
//
//function [7:0] plut_rom;
//input [3:0] clut;
//begin
//	case ( clut )
//	 0:plut_rom = 8'hxx;
//	 1:plut_rom = 8'hxx;
//	 2:plut_rom = 8'hxx;
//	 3:plut_rom = 8'hxx;
//	 4:plut_rom = 8'hxx;
//	 5:plut_rom = 8'hxx;
//	 6:plut_rom = 8'hxx;
//	 7:plut_rom = 8'hxx;
//	 8:plut_rom = 8'hxx;
//	 9:plut_rom = 8'hxx;
//	10:plut_rom = 8'hxx;
//	11:plut_rom = 8'hxx;
//	12:plut_rom = 8'hxx;
//	13:plut_rom = 8'hxx;
//	14:plut_rom = 8'hxx;
//	15:plut_rom = 8'hxx;
//	endcase
//end
//endfunction
//assign PAL_DO = plut_rom(PAL_A);
//
// ----- PALETTE RAM async. version -----


endmodule