adec.v

DE1-FPGA-Board

//
// FPGA PACMAN addredd decoder
//
// Version : beta2
//
// Copyright(c) 2002 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// 1. License
//
// This program is freeware for non-commercial use. 
// The user of this source must assume all legal 
// responsibility in the use of this program. 
// This is not GPL.
//
// 2. Guarantee 
//
// An author does no guarantee about this program.
// You can use this under your own risk. 
// 
// 3. A rule to distribute.
//   Do either 1) or 2).
//   1)Include a perfect original source.
//   2)Include all these headers , and add document of 
//     modification points
//
// 2003. 2. 6 beta2 fix cs signal with RFSH.
//
module adec(
	PCLK,
	A,
	D0I,
	n_MREQ,
	n_RD,
	n_RFSH,
	RST,
// decode out
	ROM,	// 0000-3fff , 8000-9fff,a000-bfff
	RAM,	// 4000-4fff , c000-cfff
	IN0,	// 5000-503f.R IN0
	IN1,	// 5040-507f.R IN1
	DSW1,	// 5080-50bf.W DIP switch 1
	DSW2,	// 50c0-50ff.W DIP switch 2
	WR0,	// 5040-504f.W sound accumulator / waveform
	WR1,	// 5050-505f.W sound frequency   / volume
	WR2,	// 5060-506f.W object X,Y RAM
	WDT,	// 50c0-50ff.W Watchdog timer reset
// latched output
	IRQ,	// 5000.W      IRQ enable (clear)
	SOUND_ON,// 5001.W      sound enable
	FLIP,	// 5003.W      flip
	LAMP1P,	// 5004.W      1P start lamp
	LAMP2P,	// 5005.W      2P start lamp
	COINLK,	// 5006.W      coin lockout
	COINUP	// 5007.W      coin countup
);
input PCLK;
input [15:0] A;
input D0I,n_MREQ,n_RD,n_RFSH,RST;
output ROM,RAM,IN0,IN1,DSW1,DSW2;
output WR0,WR1,WR2,WDT;
output IRQ,SOUND_ON,FLIP,LAMP1P,LAMP2P,COINLK,COINUP;

wire mreq = ~n_MREQ & n_RFSH;

//
//
//
assign ROM = mreq & ~A[14] ; // 0000-3fff,8000-bfff
assign RAM = mreq & (A[14:12] == 3'b100); // 4000-4fff,c000-cfff

//
// decoder parts 7J
//
wire port_rd = A[14] & A[12] & mreq;
wire port_wr = A[14] & A[12] & mreq;

wire out,wr012;
assign out   = port_wr & (A[7:6] == 2'b00); // 5000-503f.w
assign wr012 = port_wr & (A[7:6] == 2'b01); // 5040-507f.w
assign WDT   = port_wr & (A[7:6] == 2'b11); // 50c0-50ff.w
assign IN0   = port_rd & (A[7:6] == 2'b00); // 5000-503f.r
assign IN1   = port_rd & (A[7:6] == 2'b01); // 5040-507f.r
assign DSW1  = port_rd & (A[7:6] == 2'b10); // 5080-50bf.r
assign DSW2  = port_rd & (A[7:6] == 2'b11); // 50c0-50ff.r

//
// decoder parts 7M
//
assign WR0 = wr012 & (A[5:4] == 2'b00); // 5040-504f.w
assign WR1 = wr012 & (A[5:4] == 2'b01); // 5050-505f.w
assign WR2 = wr012 & (A[5:4] == 2'b10); // 5060-506f.w

//
// decode & latch parts 7K or 8K
//
reg irq_r,sound_on_r,flip_r,lamp1p_r,lamp2p_r,coinlk_r,coinup_r;
always @(posedge PCLK)
begin
  if(out)
  begin
	case(A[2:0])
	3'h0: irq_r <= D0I;
	3'h1: sound_on_r <= D0I;
	3'h3: flip_r <= D0I;
	3'h4: lamp1p_r <= D0I;
	3'h5: lamp2p_r <= D0I;
	3'h6: coinlk_r <= D0I;
	3'h7: coinup_r <= D0I;
	endcase
  end
end
assign IRQ    = irq_r;
assign SOUND_ON = sound_on_r;
assign FLIP   = flip_r;
assign LAMP1P = lamp1p_r;
assign LAMP2P = lamp2p_r;
assign COINLK = coinlk_r;
assign COINUP = coinup_r;

endmodule