top.qsf

DE1-FPGA-Board

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:59:59  SEPTEMBER 30, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.1
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZE_TIMING NORMAL_COMPILATION
set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
set_global_assignment -name AUTO_RESTART_CONFIGURATION ON
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE AUTO
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_location_assignment PIN_R22 -to PSW[0]
set_location_assignment PIN_D11 -to VGA_B[1]
set_location_assignment PIN_A10 -to VGA_B[2]
set_location_assignment PIN_B8 -to VGA_G[0]
set_location_assignment PIN_C10 -to VGA_G[1]
set_location_assignment PIN_B9 -to VGA_G[2]
set_location_assignment PIN_D9 -to VGA_R[0]
set_location_assignment PIN_C9 -to VGA_R[1]
set_location_assignment PIN_A7 -to VGA_R[2]
set_location_assignment PIN_A11 -to n_HSYNC
set_location_assignment PIN_B11 -to n_VSYNC
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name OUTPUT_PIN_LOAD 1 -section_id "3.3-V LVTTL"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_location_assignment PIN_AB15 -to O_ROM_CSn
set_location_assignment PIN_AA15 -to O_ROM_OEn
set_location_assignment PIN_W14 -to O_ROM_Reset_n
set_location_assignment PIN_Y14 -to O_ROM_WEn
set_location_assignment PIN_V14 -to O_ROM_AB[19]
set_location_assignment PIN_U13 -to O_ROM_AB[20]
set_location_assignment PIN_R13 -to O_ROM_AB[21]
set_location_assignment PIN_AB20 -to O_ROM_AB[0]
set_location_assignment PIN_AA14 -to O_ROM_AB[1]
set_location_assignment PIN_Y16 -to O_ROM_AB[2]
set_location_assignment PIN_R15 -to O_ROM_AB[3]
set_location_assignment PIN_T15 -to O_ROM_AB[4]
set_location_assignment PIN_U15 -to O_ROM_AB[5]
set_location_assignment PIN_V15 -to O_ROM_AB[6]
set_location_assignment PIN_W15 -to O_ROM_AB[7]
set_location_assignment PIN_R14 -to O_ROM_AB[8]
set_location_assignment PIN_Y13 -to O_ROM_AB[9]
set_location_assignment PIN_R12 -to O_ROM_AB[10]
set_location_assignment PIN_T12 -to O_ROM_AB[11]
set_location_assignment PIN_AB14 -to O_ROM_AB[12]
set_location_assignment PIN_AA13 -to O_ROM_AB[13]
set_location_assignment PIN_AB13 -to O_ROM_AB[14]
set_location_assignment PIN_AA12 -to O_ROM_AB[15]
set_location_assignment PIN_AB12 -to O_ROM_AB[16]
set_location_assignment PIN_AA20 -to O_ROM_AB[17]
set_location_assignment PIN_U14 -to O_ROM_AB[18]
set_location_assignment PIN_AB16 -to I_ROM_DB[0]
set_location_assignment PIN_AA16 -to I_ROM_DB[1]
set_location_assignment PIN_AB17 -to I_ROM_DB[2]
set_location_assignment PIN_AA17 -to I_ROM_DB[3]
set_location_assignment PIN_AB18 -to I_ROM_DB[4]
set_location_assignment PIN_AA18 -to I_ROM_DB[5]
set_location_assignment PIN_AB19 -to I_ROM_DB[6]
set_location_assignment PIN_AA19 -to I_ROM_DB[7]
set_location_assignment PIN_U22 -to DAC_L
set_location_assignment PIN_U21 -to DAC_R
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_L1 -to I_CLK_50M
set_location_assignment PIN_H15 -to PS2_CLK
set_location_assignment PIN_J14 -to PS2_DAT
set_location_assignment PIN_A3 -to I2C_SCLK
set_location_assignment PIN_B3 -to I2C_SDAT
set_location_assignment PIN_A4 -to AUD_BCLK
set_location_assignment PIN_B5 -to AUD_DACDAT
set_location_assignment PIN_A5 -to AUD_DACLRCK
set_location_assignment PIN_A6 -to AUD_ADCLRCK
set_location_assignment PIN_B4 -to AUD_XCK
set_global_assignment -name VHDL_FILE src/altera/Clock_Pll.vhd
set_global_assignment -name VHDL_FILE src/altera/alt_ram_1024_8.vhd
set_global_assignment -name VHDL_FILE src/altera/alt_ram_512_8_8.vhd
set_global_assignment -name VHDL_FILE src/altera/alt_ram_256_4.vhd
set_global_assignment -name VHDL_FILE src/altera/alt_ram_16_8.vhd
set_global_assignment -name VHDL_FILE src/altera/PAC_pal_ROM.vhd
set_global_assignment -name VHDL_FILE src/altera/PAC_clut_ROM.vhd
set_global_assignment -name VHDL_FILE src/altera/PAC_WAV_ROM.vhd
set_global_assignment -name VHDL_FILE src/WM8731/I2C_AV_Config.vhd
set_global_assignment -name VHDL_FILE src/WM8731/I2C_Controller.vhd
set_global_assignment -name VHDL_FILE src/WM8731/AUDIO_DAC.vhd
set_global_assignment -name VHDL_FILE src/ps2_keyboard.vhd
set_global_assignment -name VHDL_FILE src/KeybControl.vhd
set_global_assignment -name VERILOG_FILE src\\top.v
set_global_assignment -name VERILOG_FILE src\\clock.v
set_global_assignment -name VERILOG_FILE src\\adec.v
set_global_assignment -name VERILOG_FILE src\\inport.v
set_global_assignment -name VERILOG_FILE src\\irq.v
set_global_assignment -name VERILOG_FILE src\\video.v
set_global_assignment -name VERILOG_FILE src\\sound.v
set_global_assignment -name VERILOG_FILE src\\dac.v
set_global_assignment -name VERILOG_FILE src\\venc_vga8.v
set_global_assignment -name VERILOG_FILE src\\amemory.v
set_global_assignment -name VERILOG_FILE src\\z80ip_t.v
set_global_assignment -name VHDL_FILE t80_ip\\T80_Pack.vhd
set_global_assignment -name VHDL_FILE t80_ip\\T80_ALU.VHD
set_global_assignment -name VHDL_FILE t80_ip\\T80_MCode.vhd
set_global_assignment -name VHDL_FILE t80_ip\\T80_Reg.vhd
set_global_assignment -name VHDL_FILE t80_ip\\T80.VHD
set_global_assignment -name VHDL_FILE t80_ip\\T80as.vhd