s3demo.ucf

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "an<0>"  LOC = "E13"  ;
NET "an<1>"  LOC = "F14"  ;
NET "an<2>"  LOC = "G14"  ;
NET "an<3>"  LOC = "d14"  ;
NET "blu"  LOC = "R11"  ;
NET "btn<0>"  LOC = "M13"  ;
NET "btn<1>"  LOC = "M14"  ;
NET "btn<2>"  LOC = "L13"  ;
NET "btn<3>"  LOC = "L14"  ;
NET "grn"  LOC = "T12"  ;
NET "hs"  LOC = "R9"  ;
NET "kc"  LOC = "M16"  ;
NET "kd"  LOC = "M15"  ;
NET "led<0>"  LOC = "K12"  ;
NET "led<1>"  LOC = "P14"  ;
NET "led<2>"  LOC = "L12"  ;
NET "led<3>"  LOC = "N14"  ;
NET "led<4>"  LOC = "P13"  ;
NET "led<5>"  LOC = "N12"  ;
NET "led<6>"  LOC = "P12"  ;
NET "led<7>"  LOC = "P11"  ;
NET "mclk"  LOC = "T9"  ;
NET "red"  LOC = "R12"  ;
NET "ssg<0>"  LOC = "E14"  ;
NET "ssg<1>"  LOC = "G13"  ;
NET "ssg<2>"  LOC = "N15"  ;
NET "ssg<3>"  LOC = "P15"  ;
NET "ssg<4>"  LOC = "R16"  ;
NET "ssg<5>"  LOC = "F13"  ;
NET "ssg<6>"  LOC = "N16"  ;
NET "ssg<7>"  LOC = "P16"  ;
NET "swt<0>"  LOC = "F12"  ;
NET "swt<1>"  LOC = "G12"  ;
NET "swt<2>"  LOC = "H14"  ;
NET "swt<3>"  LOC = "H13"  ;
NET "swt<4>"  LOC = "J14"  ;
NET "swt<5>"  LOC = "J13"  ;
NET "swt<6>"  LOC = "K14"  ;
NET "swt<7>"  LOC = "K13"  ;
NET "vs"  LOC = "T10"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE