__projnav.log

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
 16x7-bit ROM                      : 2
# Counters                         : 5
 24-bit up counter                 : 1
 10-bit up counter                 : 2
 13-bit up counter                 : 1
 4-bit up counter                  : 1
# Registers                        : 28
 1-bit register                    : 27
 8-bit register                    : 1
# Comparators                      : 4
 10-bit comparator greater         : 2
 10-bit comparator less            : 2
# Multiplexers                     : 9
 4-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 7

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <s3demo> ...

Optimizing unit <vgaController> ...

Optimizing unit <keyboardVhdl> ...
Loading device for application Xst from file '3s200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block s3demo, actual ratio is 4.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-5 

 Number of Slices:                      66  out of   1920     3%  
 Number of Slice Flip Flops:            96  out of   3840     2%  
 Number of 4 input LUTs:               108  out of   3840     2%  
 Number of bonded IOBs:                 39  out of    173    22%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
mclk                               | BUFGP                  | 38    |
clkdiv_23:Q                        | NONE                   | 4     |
vga1_clkdiv:Q                      | NONE                   | 21    |
kb1_KCI:Q                          | NONE                   | 29    |
kb1_clkDiv_3:Q                     | NONE                   | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 7.120ns (Maximum Frequency: 140.449MHz)
   Minimum input arrival time before clock: 2.095ns
   Maximum output required time after clock: 7.812ns
   Maximum combinational path delay: 7.962ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\xilinx-projects\working\s3demo/_ngo
-uc S3demo.ucf -p xc3s200-ft256-5 s3demo.ngc s3demo.ngd 

Reading NGO file "C:/Xilinx-Projects/Working/S3Demo/s3demo.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "S3demo.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40116 kilobytes

Writing NGD file "s3demo.ngd" ...

Writing NGDBUILD log file "s3demo.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s200ft256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          94 out of   3,840    2%
  Number of 4 input LUTs:              54 out of   3,840    1%
Logic Distribution:
  Number of occupied Slices:                           75 out of   1,920    3%
    Number of Slices containing only related logic:      75 out of      75  100%
    Number of Slices containing unrelated logic:          0 out of      75    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            107 out of   3,840    2%
  Number used as logic:                 54
  Number used as a route-thru:          53
  Number of bonded IOBs:               40 out of     173   23%
    IOB Flip Flops:                     2
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  1,434
Additional JTAG gate count for IOBs:  1,920
Peak Memory Usage:  68 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "s3demo_map.mrp" for details.
Completed process "Map".

Mapping Module s3demo . . .
MAP command line:
map -intstyle ise -p xc3s200-ft256-5 -cm area -pr b -k 4 -c 100 -tx off -o s3demo_map.ncd s3demo.ngd s3demo.pcf
Mapping Module s3demo: DONE



Started process "Place & Route".





Constraints file: s3demo.pcf

Loading device database for application Par from file "s3demo_map.ncd".
   "s3demo" is an NCD, version 2.38, device xc3s200, package ft256, speed -5
Loading device for application Par from file '3s200.nph' in environment
C:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-09.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            40 out of 173    23%
      Number of LOCed External IOBs   40 out of 40    100%

   Number of Slices                   75 out of 1920    3%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9898a1) REAL time: 3 secs 

.
Phase 3.8
..
Phase 3.8 (Checksum:99204f) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 3 secs 

Writing design to file s3demo.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 429 unrouted;       REAL time: 3 secs 

Phase 2: 379 unrouted;       REAL time: 4 secs 

Phase 3: 140 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|        mclk_BUFGP       |  BUFGMUX0| No   |   20 |  0.002     |  0.882      |
+-------------------------+----------+------+------+------------+-------------+
|        clkdiv<23>       |   Local  |      |    3 |  0.000     |  1.389      |
+-------------------------+----------+------+------+------------+-------------+
|       vga1_clkdiv       |   Local  |      |   12 |  0.811     |  1.765      |
+-------------------------+----------+------+------+------------+-------------+
|     kb1_clkDiv<3>       |   Local  |      |    5 |  0.032     |  2.045      |
+-------------------------+----------+------+------+------------+-------------+
|           kb1_KCI       |   Local  |      |   15 |  0.016     |  1.634      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  58 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file s3demo.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Mon Jul 12 10:32:20 2004
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module s3demo . . .
PAR command line: par -w -intstyle ise -ol std -t 1 s3demo_map.ncd s3demo.ncd s3demo.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/S3DEMO is now defined in a different file: was C:/Xilinx-Projects/Working/S3Demo/S3demo.vhd, now is G:/资料/Spartan-3/S3Demo/S3demo.vhd
WARNING:HDLParsers:3215 - Unit work/S3DEMO/BEHAVIORAL is now defined in a different file: was C:/Xilinx-Projects/Working/S3Demo/S3demo.vhd, now is G:/资料/Spartan-3/S3Demo/S3demo.vhd
WARNING:HDLParsers:3215 - Unit work/KEYBOARDVHDL is now defined in a different file: was C:/Xilinx-Projects/Working/S3Demo/kb2vhdl.vhd, now is G:/资料/Spartan-3/S3Demo/kb2vhdl.vhd
WARNING:HDLParsers:3215 - Unit work/KEYBOARDVHDL/BEHAVIORAL is now defined in a different file: was C:/Xilinx-Projects/Working/S3Demo/kb2vhdl.vhd, now is G:/资料/Spartan-3/S3Demo/kb2vhdl.vhd
WARNING:HDLParsers:3215 - Unit work/VGACONTROLLER is now defined in a different file: was C:/Xilinx-Projects/Working/S3Demo/vga_main.vhd, now is G:/资料/Spartan-3/S3Demo/vga_main.vhd
WARNING:HDLParsers:3215 - Unit work/VGACONTROLLER/BEHAVIORAL is now defined in a different file: was C:/Xilinx-Projects/Working/S3Demo/vga_main.vhd, now is G:/资料/Spartan-3/S3Demo/vga_main.vhd
Compiling vhdl file G:/资料/Spartan-3/S3Demo/vga_main.vhd in Library work.
Architecture behavioral of Entity vgacontroller is up to date.
Compiling vhdl file G:/资料/Spartan-3/S3Demo/kb2vhdl.vhd in Library work.
Architecture behavioral of Entity keyboardvhdl is up to date.
Compiling vhdl file G:/资料/Spartan-3/S3Demo/S3demo.vhd in Library work.
Architecture behavioral of Entity s3demo is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <s3demo> (Architecture <behavioral>).
Entity <s3demo> analyzed. Unit <s3demo> generated.

Analyzing Entity <vgaController> (Architecture <behavioral>).
Entity <vgaController> analyzed. Unit <vgaController> generated.

Analyzing Entity <keyboardVhdl> (Architecture <behavioral>).
Entity <keyboardVhdl> analyzed. Unit <keyboardVhdl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <keyboardVhdl>.
    Related source file is G:/资料/Spartan-3/S3Demo/kb2vhdl.vhd.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <shiftRegSig2<8>> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 16x7-bit ROM for signal <sseg>.
    Found 13-bit up counter for signal <clkDiv>.
    Found 1-bit register for signal <DFF1>.
    Found 1-bit register for signal <DFF2>.
    Found 1-bit register for signal <KCI>.
    Found 1-bit register for signal <KDI>.
    Found 11-bit register for signal <shiftRegSig1>.
    Found 10-bit register for signal <shiftRegSig2>.
    Found 8-bit register for signal <WaitReg>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).