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用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx-Projects/Working/S3Demo/vga_main.vhd in Library work.
Entity <vgaController> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/Xilinx-Projects/Working/S3Demo/kb2vhdl.vhd in Library work.
Entity <keyboardVhdl> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/Xilinx-Projects/Working/S3Demo/S3demo.vhd in Library work.
Entity <Pegasusdemo> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <pegasusdemo> (Architecture <Behavioral>).
Entity <pegasusdemo> analyzed. Unit <pegasusdemo> generated.

Analyzing Entity <vgaController> (Architecture <behavioral>).
Entity <vgaController> analyzed. Unit <vgaController> generated.

Analyzing Entity <keyboardVhdl> (Architecture <behavioral>).
Entity <keyboardVhdl> analyzed. Unit <keyboardVhdl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <keyboardVhdl>.
    Related source file is C:/Xilinx-Projects/Working/S3Demo/kb2vhdl.vhd.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <shiftRegSig2<8>> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 16x7-bit ROM for signal <sseg>.
    Found 13-bit up counter for signal <clkDiv>.
    Found 1-bit register for signal <DFF1>.
    Found 1-bit register for signal <DFF2>.
    Found 1-bit register for signal <KCI>.
    Found 1-bit register for signal <KDI>.
    Found 11-bit register for signal <shiftRegSig1>.
    Found 10-bit register for signal <shiftRegSig2>.
    Found 8-bit register for signal <WaitReg>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <keyboardVhdl> synthesized.


Synthesizing Unit <vgaController>.
    Related source file is C:/Xilinx-Projects/Working/S3Demo/vga_main.vhd.
    Found 10-bit comparator less for signal <$n0017> created at line 101.
    Found 10-bit comparator greater for signal <$n0018> created at line 101.
    Found 10-bit comparator less for signal <$n0019> created at line 101.
    Found 10-bit comparator greater for signal <$n0020> created at line 101.
    Found 1-bit register for signal <clkdiv>.
    Found 10-bit up counter for signal <hc>.
    Found 10-bit up counter for signal <vc>.
    Found 1-bit register for signal <vsenable>.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <vgaController> synthesized.


Synthesizing Unit <pegasusdemo>.
    Related source file is C:/Xilinx-Projects/Working/S3Demo/S3demo.vhd.
    Found 16x7-bit ROM for signal <dig>.
    Found 24-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <cntr>.
    Found 11 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred  11 Multiplexer(s).
Unit <pegasusdemo> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
 16x7-bit ROM                      : 2
# Counters                         : 5
 24-bit up counter                 : 1
 10-bit up counter                 : 2
 13-bit up counter                 : 1
 4-bit up counter                  : 1
# Registers                        : 28
 1-bit register                    : 27
 8-bit register                    : 1
# Comparators                      : 4
 10-bit comparator greater         : 2
 10-bit comparator less            : 2
# Multiplexers                     : 9
 4-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 7

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <pegasusdemo> ...

Optimizing unit <vgaController> ...

Optimizing unit <keyboardVhdl> ...
Loading device for application Xst from file '3s200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pegasusdemo, actual ratio is 4.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-5 

 Number of Slices:                      66  out of   1920     3%  
 Number of Slice Flip Flops:            96  out of   3840     2%  
 Number of 4 input LUTs:               108  out of   3840     2%  
 Number of bonded IOBs:                 39  out of    173    22%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
mclk                               | BUFGP                  | 38    |
clkdiv_23:Q                        | NONE                   | 4     |
vga1_clkdiv:Q                      | NONE                   | 21    |
kb1_KCI:Q                          | NONE                   | 29    |
kb1_clkDiv_3:Q                     | NONE                   | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 7.120ns (Maximum Frequency: 140.449MHz)
   Minimum input arrival time before clock: 2.095ns
   Maximum output required time after clock: 7.812ns
   Maximum combinational path delay: 7.962ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\xilinx-projects\working\s3demo/_ngo
-uc S3demo.ucf -p xc3s200-ft256-5 pegasusdemo.ngc pegasusdemo.ngd 

Reading NGO file "C:/Xilinx-Projects/Working/S3Demo/pegasusdemo.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "S3demo.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40116 kilobytes

Writing NGD file "pegasusdemo.ngd" ...

Writing NGDBUILD log file "pegasusdemo.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\xilinx-projects\working\s3demo/_ngo
-uc S3demo.ucf -p xc3s200-ft256-5 pegasusdemo.ngc pegasusdemo.ngd 

Reading NGO file "C:/Xilinx-Projects/Working/S3Demo/pegasusdemo.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "S3demo.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40116 kilobytes

Writing NGD file "pegasusdemo.ngd" ...

Writing NGDBUILD log file "pegasusdemo.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx-Projects/Working/S3Demo/vga_main.vhd in Library work.
Architecture behavioral of Entity vgacontroller is up to date.
Compiling vhdl file C:/Xilinx-Projects/Working/S3Demo/kb2vhdl.vhd in Library work.
Architecture behavioral of Entity keyboardvhdl is up to date.
Compiling vhdl file C:/Xilinx-Projects/Working/S3Demo/S3demo.vhd in Library work.
Architecture behavioral of Entity pegasusdemo is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <pegasusdemo> (Architecture <behavioral>).
Entity <pegasusdemo> analyzed. Unit <pegasusdemo> generated.

Analyzing Entity <vgaController> (Architecture <behavioral>).
Entity <vgaController> analyzed. Unit <vgaController> generated.

Analyzing Entity <keyboardVhdl> (Architecture <behavioral>).
Entity <keyboardVhdl> analyzed. Unit <keyboardVhdl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <keyboardVhdl>.
    Related source file is C:/Xilinx-Projects/Working/S3Demo/kb2vhdl.vhd.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <shiftRegSig2<8>> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 16x7-bit ROM for signal <sseg>.
    Found 13-bit up counter for signal <clkDiv>.
    Found 1-bit register for signal <DFF1>.
    Found 1-bit register for signal <DFF2>.
    Found 1-bit register for signal <KCI>.
    Found 1-bit register for signal <KDI>.
    Found 11-bit register for signal <shiftRegSig1>.
    Found 10-bit register for signal <shiftRegSig2>.
    Found 8-bit register for signal <WaitReg>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <keyboardVhdl> synthesized.


Synthesizing Unit <vgaController>.
    Related source file is C:/Xilinx-Projects/Working/S3Demo/vga_main.vhd.
    Found 10-bit comparator less for signal <$n0017> created at line 101.
    Found 10-bit comparator greater for signal <$n0018> created at line 101.
    Found 10-bit comparator less for signal <$n0019> created at line 101.
    Found 10-bit comparator greater for signal <$n0020> created at line 101.
    Found 1-bit register for signal <clkdiv>.
    Found 10-bit up counter for signal <hc>.
    Found 10-bit up counter for signal <vc>.
    Found 1-bit register for signal <vsenable>.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <vgaController> synthesized.


Synthesizing Unit <pegasusdemo>.
    Related source file is C:/Xilinx-Projects/Working/S3Demo/S3demo.vhd.
    Found 16x7-bit ROM for signal <dig>.
    Found 24-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <cntr>.
    Found 11 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred  11 Multiplexer(s).
Unit <pegasusdemo> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
 16x7-bit ROM                      : 2
# Counters                         : 5
 24-bit up counter                 : 1
 10-bit up counter                 : 2
 13-bit up counter                 : 1
 4-bit up counter                  : 1
# Registers                        : 28
 1-bit register                    : 27
 8-bit register                    : 1
# Comparators                      : 4
 10-bit comparator greater         : 2
 10-bit comparator less            : 2
# Multiplexers                     : 9
 4-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 7

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <pegasusdemo> ...