s3demo.syr

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
mclk                               | BUFGP                  | 38    |
clkdiv_23:Q                        | NONE                   | 4     |
vga1_clkdiv:Q                      | NONE                   | 21    |
kb1_KCI:Q                          | NONE                   | 29    |
kb1_clkDiv_3:Q                     | NONE                   | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 7.120ns (Maximum Frequency: 140.449MHz)
   Minimum input arrival time before clock: 2.095ns
   Maximum output required time after clock: 7.812ns
   Maximum combinational path delay: 7.962ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'mclk'
Delay:               3.963ns (Levels of Logic = 25)
  Source:            clkdiv_0 (FF)
  Destination:       clkdiv_23 (FF)
  Source Clock:      mclk rising
  Destination Clock: mclk rising

  Data Path: clkdiv_0 to clkdiv_23
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.626   0.240  clkdiv_0 (clkdiv_0)
     LUT1:I0->O            2   0.479   0.000  clkdiv_LPM_COUNTER_4__n0000<0>lut (clkdiv_N1146)
     MUXCY:S->O            1   0.435   0.000  clkdiv_LPM_COUNTER_4__n0000<0>cy (clkdiv_LPM_COUNTER_4__n0000<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<1>cy (clkdiv_LPM_COUNTER_4__n0000<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<2>cy (clkdiv_LPM_COUNTER_4__n0000<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<3>cy (clkdiv_LPM_COUNTER_4__n0000<3>_cyo)
     MUXCY:CI->O           1   0.055   0.000  clkdiv_LPM_COUNTER_4__n0000<4>cy (clkdiv_LPM_COUNTER_4__n0000<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<5>cy (clkdiv_LPM_COUNTER_4__n0000<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<6>cy (clkdiv_LPM_COUNTER_4__n0000<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<7>cy (clkdiv_LPM_COUNTER_4__n0000<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<8>cy (clkdiv_LPM_COUNTER_4__n0000<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<9>cy (clkdiv_LPM_COUNTER_4__n0000<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<10>cy (clkdiv_LPM_COUNTER_4__n0000<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<11>cy (clkdiv_LPM_COUNTER_4__n0000<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<12>cy (clkdiv_LPM_COUNTER_4__n0000<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<13>cy (clkdiv_LPM_COUNTER_4__n0000<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<14>cy (clkdiv_LPM_COUNTER_4__n0000<14>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<15>cy (clkdiv_LPM_COUNTER_4__n0000<15>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<16>cy (clkdiv_LPM_COUNTER_4__n0000<16>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<17>cy (clkdiv_LPM_COUNTER_4__n0000<17>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<18>cy (clkdiv_LPM_COUNTER_4__n0000<18>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<19>cy (clkdiv_LPM_COUNTER_4__n0000<19>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<20>cy (clkdiv_LPM_COUNTER_4__n0000<20>_cyo)
     MUXCY:CI->O           1   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<21>cy (clkdiv_LPM_COUNTER_4__n0000<21>_cyo)
     MUXCY:CI->O           0   0.056   0.000  clkdiv_LPM_COUNTER_4__n0000<22>cy (clkdiv_LPM_COUNTER_4__n0000<22>_cyo)
     XORCY:CI->O           1   0.786   0.000  clkdiv_LPM_COUNTER_4__n0000<23>_xor (clkdiv__n0000<23>)
     FD:D                      0.176          clkdiv_23
    ----------------------------------------
    Total                      3.963ns (3.723ns logic, 0.240ns route)
                                       (93.9% logic, 6.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clkdiv_23:Q'
Delay:               3.491ns (Levels of Logic = 1)
  Source:            cntr_0 (FF)
  Destination:       cntr_3 (FF)
  Source Clock:      clkdiv_23:Q rising
  Destination Clock: clkdiv_23:Q rising

  Data Path: cntr_0 to cntr_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             12   0.626   0.865  cntr_0 (cntr_0)
     LUT4:I2->O            4   0.479   0.629  _n00011 (_n0001)
     FDR:R                     0.892          cntr_0
    ----------------------------------------
    Total                      3.491ns (1.997ns logic, 1.494ns route)
                                       (57.2% logic, 42.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'vga1_clkdiv:Q'
Delay:               4.405ns (Levels of Logic = 2)
  Source:            vga1_hc_8 (FF)
  Destination:       vga1_hc_9 (FF)
  Source Clock:      vga1_clkdiv:Q rising
  Destination Clock: vga1_clkdiv:Q rising

  Data Path: vga1_hc_8 to vga1_hc_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   0.626   0.658  vga1_hc_8 (vga1_hc_8)
     LUT4:I0->O            2   0.479   0.465  vga1_SF226934_SW0 (N4931)
     LUT4:I2->O           10   0.479   0.806  vga1_SF226934 (vga1_SF2269)
     FDR:R                     0.892          vga1_hc_8
    ----------------------------------------
    Total                      4.405ns (2.476ns logic, 1.929ns route)
                                       (56.2% logic, 43.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'kb1_KCI:Q'
Delay:               3.560ns (Levels of Logic = 2)
  Source:            kb1_shiftRegSig2_2 (FF)
  Destination:       kb1_WaitReg_7 (FF)
  Source Clock:      kb1_KCI:Q falling
  Destination Clock: kb1_KCI:Q rising

  Data Path: kb1_shiftRegSig2_2 to kb1_WaitReg_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   0.626   0.465  kb1_shiftRegSig2_2 (kb1_shiftRegSig2_2)
     LUT4:I1->O            1   0.479   0.240  kb1__n000017 (CHOICE264)
     LUT2:I1->O            8   0.479   0.747  kb1__n000018 (kb1__n0000)
     FDCE:CE                   0.524          kb1_WaitReg_0
    ----------------------------------------
    Total                      3.560ns (2.108ns logic, 1.452ns route)
                                       (59.2% logic, 40.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'kb1_clkDiv_3:Q'
Delay:               1.042ns (Levels of Logic = 0)
  Source:            kb1_DFF2 (FF)
  Destination:       kb1_KCI (FF)
  Source Clock:      kb1_clkDiv_3:Q rising
  Destination Clock: kb1_clkDiv_3:Q rising

  Data Path: kb1_DFF2 to kb1_KCI
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.626   0.240  kb1_DFF2 (kb1_DFF2)
     FDC:D                     0.176          kb1_KCI
    ----------------------------------------
    Total                      1.042ns (0.802ns logic, 0.240ns route)
                                       (77.0% logic, 23.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'kb1_clkDiv_3:Q'
Offset:              2.095ns (Levels of Logic = 1)
  Source:            kc (PAD)
  Destination:       kb1_DFF2 (FF)
  Destination Clock: kb1_clkDiv_3:Q rising

  Data Path: kc to kb1_DFF2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.679   0.240  kc_IBUF (kc_IBUF)
     FDC:D                     0.176          kb1_DFF2
    ----------------------------------------
    Total                      2.095ns (1.855ns logic, 0.240ns route)
                                       (88.5% logic, 11.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'vga1_clkdiv:Q'
Offset:              7.681ns (Levels of Logic = 4)
  Source:            vga1_hc_9 (FF)
  Destination:       grn (PAD)
  Source Clock:      vga1_clkdiv:Q rising

  Data Path: vga1_hc_9 to grn
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   0.626   0.658  vga1_hc_9 (vga1_hc_9)
     LUT4:I0->O            1   0.479   0.240  vga1__n001027 (CHOICE203)
     LUT4:I3->O            1   0.479   0.240  vga1__n001036_SW0 (N4950)
     LUT4:I3->O            1   0.479   0.240  vga1__n001036 (grn_OBUF)
     OBUF:I->O                 4.240          grn_OBUF (grn)
    ----------------------------------------
    Total                      7.681ns (6.303ns logic, 1.378ns route)
                                       (82.1% logic, 17.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk'
Offset:              7.812ns (Levels of Logic = 4)
  Source:            kb1_clkDiv_12 (FF)
  Destination:       ssg<6> (PAD)
  Source Clock:      mclk rising

  Data Path: kb1_clkDiv_12 to ssg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               7   0.626   0.717  kb1_clkDiv_12 (kb1_clkDiv_12)
     LUT3:I0->O            7   0.479   0.717  kb1_Mmux_MUXOUT_Result<3>1 (kb1_MUXOUT<3>)
     LUT4:I3->O            1   0.479   0.000  Mmux_ssg<0>_Result1_G (N4967)
     MUXF5:I1->O           1   0.314   0.240  Mmux_ssg<0>_Result1 (ssg_0_OBUF)
     OBUF:I->O                 4.240          ssg_0_OBUF (ssg<0>)
    ----------------------------------------
    Total                      7.812ns (6.138ns logic, 1.674ns route)
                                       (78.6% logic, 21.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkdiv_23:Q'
Offset:              6.764ns (Levels of Logic = 3)
  Source:            cntr_0 (FF)
  Destination:       ssg<6> (PAD)
  Source Clock:      clkdiv_23:Q rising

  Data Path: cntr_0 to ssg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             12   0.626   0.865  cntr_0 (cntr_0)
     LUT4:I0->O            1   0.479   0.000  Mmux_ssg<5>_Result1_F (N4970)
     MUXF5:I0->O           1   0.314   0.240  Mmux_ssg<5>_Result1 (ssg_5_OBUF)
     OBUF:I->O                 4.240          ssg_5_OBUF (ssg<5>)
    ----------------------------------------
    Total                      6.764ns (5.659ns logic, 1.105ns route)
                                       (83.7% logic, 16.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'kb1_KCI:Q'
Offset:              7.335ns (Levels of Logic = 4)
  Source:            kb1_WaitReg_0 (FF)
  Destination:       ssg<6> (PAD)
  Source Clock:      kb1_KCI:Q rising

  Data Path: kb1_WaitReg_0 to ssg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.626   0.240  kb1_WaitReg_0 (kb1_WaitReg_0)
     LUT3:I1->O            7   0.479   0.717  kb1_Mmux_MUXOUT_Result<0>1 (kb1_MUXOUT<0>)
     LUT4:I0->O            1   0.479   0.000  Mmux_ssg<0>_Result1_G (N4967)
     MUXF5:I1->O           1   0.314   0.240  Mmux_ssg<0>_Result1 (ssg_0_OBUF)
     OBUF:I->O                 4.240          ssg_0_OBUF (ssg<0>)
    ----------------------------------------
    Total                      7.335ns (6.138ns logic, 1.197ns route)
                                       (83.7% logic, 16.3% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               7.962ns (Levels of Logic = 3)
  Source:            btn<0> (PAD)
  Destination:       an<0> (PAD)

  Data Path: btn<0> to an<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            35   1.679   1.324  btn_0_IBUF (btn_0_IBUF)
     LUT3:I2->O            1   0.479   0.240  Mmux_an_Result<0>1 (an_0_OBUF)
     OBUF:I->O                 4.240          an_0_OBUF (an<0>)
    ----------------------------------------
    Total                      7.962ns (6.398ns logic, 1.564ns route)
                                       (80.4% logic, 19.6% route)

=========================================================================
CPU : 10.25 / 11.69 s | Elapsed : 10.00 / 11.00 s
 
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Total memory usage is 72476 kilobytes