s3demo.syr

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: s3demo.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : s3demo.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : s3demo
Output Format                      : NGC
Target Device                      : xc3s400-5-ft256

---- Source Options
Top Module Name                    : s3demo
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : s3demo.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/资料/Spartan-3/S3Demo/vga_main.vhd in Library work.
Architecture behavioral of Entity vgacontroller is up to date.
Compiling vhdl file G:/资料/Spartan-3/S3Demo/kb2vhdl.vhd in Library work.
Architecture behavioral of Entity keyboardvhdl is up to date.
Compiling vhdl file G:/资料/Spartan-3/S3Demo/S3demo.vhd in Library work.
Architecture behavioral of Entity s3demo is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <s3demo> (Architecture <behavioral>).
Entity <s3demo> analyzed. Unit <s3demo> generated.

Analyzing Entity <vgaController> (Architecture <behavioral>).
Entity <vgaController> analyzed. Unit <vgaController> generated.

Analyzing Entity <keyboardVhdl> (Architecture <behavioral>).
Entity <keyboardVhdl> analyzed. Unit <keyboardVhdl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <keyboardVhdl>.
    Related source file is G:/资料/Spartan-3/S3Demo/kb2vhdl.vhd.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <shiftRegSig2<8>> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 16x7-bit ROM for signal <sseg>.
    Found 13-bit up counter for signal <clkDiv>.
    Found 1-bit register for signal <DFF1>.
    Found 1-bit register for signal <DFF2>.
    Found 1-bit register for signal <KCI>.
    Found 1-bit register for signal <KDI>.
    Found 11-bit register for signal <shiftRegSig1>.
    Found 10-bit register for signal <shiftRegSig2>.
    Found 8-bit register for signal <WaitReg>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <keyboardVhdl> synthesized.


Synthesizing Unit <vgaController>.
    Related source file is G:/资料/Spartan-3/S3Demo/vga_main.vhd.
    Found 10-bit comparator less for signal <$n0017> created at line 101.
    Found 10-bit comparator greater for signal <$n0018> created at line 101.
    Found 10-bit comparator less for signal <$n0019> created at line 101.
    Found 10-bit comparator greater for signal <$n0020> created at line 101.
    Found 1-bit register for signal <clkdiv>.
    Found 10-bit up counter for signal <hc>.
    Found 10-bit up counter for signal <vc>.
    Found 1-bit register for signal <vsenable>.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <vgaController> synthesized.


Synthesizing Unit <s3demo>.
    Related source file is G:/资料/Spartan-3/S3Demo/S3demo.vhd.
    Found 16x7-bit ROM for signal <dig>.
    Found 24-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <cntr>.
    Found 11 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred  11 Multiplexer(s).
Unit <s3demo> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
 16x7-bit ROM                      : 2
# Counters                         : 5
 24-bit up counter                 : 1
 10-bit up counter                 : 2
 13-bit up counter                 : 1
 4-bit up counter                  : 1
# Registers                        : 28
 1-bit register                    : 27
 8-bit register                    : 1
# Comparators                      : 4
 10-bit comparator greater         : 2
 10-bit comparator less            : 2
# Multiplexers                     : 9
 4-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 7

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <s3demo> ...

Optimizing unit <vgaController> ...

Optimizing unit <keyboardVhdl> ...
Loading device for application Xst from file '3s400.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block s3demo, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : s3demo.ngr
Top Level Output File Name         : s3demo
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 40

Macro Statistics :
# ROMs                             : 2
#      16x7-bit ROM                : 2
# Registers                        : 33
#      1-bit register              : 27
#      4-bit register              : 5
#      8-bit register              : 1
# Multiplexers                     : 9
#      2-to-1 multiplexer          : 9
# Comparators                      : 4
#      10-bit comparator greater   : 2
#      10-bit comparator less      : 2

Cell Usage :
# BELS                             : 223
#      GND                         : 1
#      LUT1                        : 58
#      LUT2                        : 4
#      LUT3                        : 11
#      LUT4                        : 34
#      LUT4_L                      : 1
#      MUXCY                       : 53
#      MUXF5                       : 7
#      VCC                         : 1
#      XORCY                       : 53
# FlipFlops/Latches                : 96
#      FD                          : 37
#      FDC                         : 4
#      FDC_1                       : 21
#      FDCE                        : 8
#      FDR                         : 16
#      FDRE                        : 10
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 39
#      IBUF                        : 14
#      OBUF                        : 25
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400ft256-5 

 Number of Slices:                      66  out of   3584     1%  
 Number of Slice Flip Flops:            96  out of   7168     1%  
 Number of 4 input LUTs:               108  out of   7168     1%  
 Number of bonded IOBs:                 39  out of    173    22%  
 Number of GCLKs:                        1  out of      8    12%